In this paper, we describe improved hardware to connect a semiconductor tester or applications board to a laser scanning microscope (LSM) for performing dynamic laser stimulation (DLS). The hardware, called DXGlue, simplifies the DLS workflow and enables new applications. We describe its precise monitoring of the fail rate and fail mode, its use for time resolved DLS and the enabling of long test loops with short laser dwell times.

In most of the non-destructive electrical fault isolation cases, techniques such as DLS, Photon Emission, LIT, OBIRCH indicate a fault location directly. But relying on just one of these techniques for marginal failure mechanism is not enough for better fault localization. When Failure Analysis (FA) engineers encounter high NDF (No Defect Found) rates, by using only one of the techniques, they may need to consider the relationship between the responded locations by different techniques and fail phenomenon for better defect isolation. This paper talks about how a responded DLS location does not always indicate a fault location and how LVP data collected using DLS location can pin point the real defect location.

Dynamic Laser Stimulation using Continuous Wave (CW) Lasers has been a very important technique in fault isolating soft failures due to process defects and design speed paths in microprocessors. However, the rapid scaling down of the process technologies and the high density of logic laid out in silicon has made it difficult to precisely fault isolate using a conventional continuous wave laser which has a laser spot size of about ~300nm. Also, the remnant effects of a CW laser DLS like banding due to n-well interactions make it further difficult to achieve high resolution fault isolation. In this paper we discuss how by using a modulated pico-second pulsed laser, a DLS suspect is isolated to cell internal nets, which using a CW laser spanned across multiple cells. This is achieved by modulating the pulsed laser using an Electro-optical modulator and restricting the stimulation to only those parts of a test-pattern where the signal propagation occurs. Also, by synchronizing the pulsed laser with the clock of the test-program and changing the laser pulse delivery in time, high stimulation levels were achieved without being invasive. This revealed extra data points (DLS sites) that can help with making precisely accurate Physical FA plans that reduce turnaround time and also ensure high success rates. Specifically, in the case of a bridging defect between two nets wherein DLS sites were only seen on the victim net using conventional CW laser, the time resolved pulsed laser revealed DLS sites on the aggressor net as well. This confirmed the bridging between the two nets since the aggressor net was not electrically connected with the victim net. We discuss in detail how the DLS sites play their role in framing the perfect Physical FA plan. A detailed study of the resolution achieved using time resolved pulsed laser and its comparison with the same using a CW laser is shown on 14nm FinFET technology.

Limitations of backside optical techniques for failure analysis of dynamically activated devices have underlined the need to extend the capabilities of Dynamic Laser Stimulation techniques (DLS). DLS techniques provide a precise localization of the dynamically failing area, but it lacks timing information as the fault is often related to a specific test vector. Optical probing techniques such as TRE and LVP [1, 2] are hardly applicable on cases with long test loop and for which no preliminary information is available on the time window of interest. Defect localization and electrical tests can be coupled in order to provide more accurate information about the failure, especially vector information in addition to x and y localization. We have developed a Full Dynamic Laser Stimulation (F-DLS) approach based on laser modulation by electro optic modulator to face this challenge. The purpose of this paper is to present DLS limitations, our motivations, comparisons with other DLS extensions, FDLS implementation on our system, application example and future F-DLS developments.

This paper presents the use of Dynamic Laser Stimulation (DLS) and Time-Resolved DLS (TR-DLS) to provide fail site localization and complementary information on a failed embedded memory IC. In this study, an embedded dual port RAM within a 90nm IC that failed one of the Memory Built-In Self Tests (MBISTs) was investigated. This technique rapidly localized the failing area within the memory read/write circuitry. The TR-DLS provided maps for each operation of the MBIST pattern. With this information, the failure was clearly identified as a read operation failure. The TR-DLS technique also provided much refined site signature (down to just one net) within the sense amp of the Port B of the dual port RAM. This information provided very specific indication on how to improve the operation of that particular sense amp circuitry within the dual port RAM Memory.

Dynamic Laser Stimulation (DLS) technique have met with great success over the past few years in helping failure analysis engineer to tackle different type of soft failures. DLS is widely applied to devices presenting an abnormal behavior for any electrical parameter, such as operating voltage and frequency. This paper showcase another successful implementation of DLS technique, combined with design analysis to reveal the root cause for SRAM soft failure.

The increasing electrical design and physical complexity of semiconductor devices, especially in the analog and mixed signal (AMS) applications, directly influences the development and evolution of fault isolation techniques. One of these techniques is Dynamic Laser Stimulation (DLS) which is widely used in the industry for effective identification of subtle failure mechanisms and soft defects especially for AC signal-related failures [1, 2]. However, for analysis of some complex AMS IC failure modes, the tool’s standard setup may not always be compatible with the biasing requirements of the device. For example, the setup would typically require expensive and intricate test systems (i.e. Automatic test equipment (ATE), SCAN tester, etc.) to be interfaced with the DLS tool for the analysis to be feasible and successful [3, 4]. This paper presents simple and practical techniques to implement DLS without the need for an expensive test support system. These techniques were applied in three different FA cases involving AMS ICs with complex and temperature-dependent failure modes. The results of subsequent analysis indicated success in isolating the exact defect sites.

With the ever decreasing trend in accessibility to hardware tools, the need for software tools is becoming greater than ever for IC fault diagnosis. In this paper, we present a process of studying the limitations and capabilities of fault diagnosis using automated Diagnosis tools, such as FastScan™, as applied to a programmable, parallel processing DSP, The Multimedia Video Processor (TMS320C80). Starting with a brief description of the MVP, we describe how FastScan™ is integrated for supporting fault diagnosis. For establishing the effectiveness of FactScan™ as a diagnostic tool, both the simulation and manufacturing modes of evaluation were done. In simulation mode, both the fault model and the heuristics used by the fault diagnosis software are tested by inserting known defects using a focused ion beam (FIB), machine. This process is then repeated with unknown defects in unknown locations. Experiments on several chips demonstrate the value of the tool and its limitations in relation to detection of classic stuck-at faults and some realistic faults, such as bridging defects.

Static Random-Access Memory (SRAM) failure analysis (FA) is important during chip-level reliability evaluation and yield improvement. Single-bit, paired-bit, and quad-bit failures—whose defect should be at the failing bit-cell locations—can be directly sent for Physical Failure Analysis (PFA). For one or multiple row/column failures with too large of a suspected circuit area, more detailed fault isolation is required before PFA. Currently, Photon Emission Microscopy (PEM) is the most commonly used Electrical Failure Analysis (EFA) technique for this kind of fail [1]. Soft-Defect Localization / Dynamic Laser Stimulation (SDL/DLS) can also be applied on soft (Vmin) row/column fails for further isolation [2]. However, some failures do not have abnormal emission spots or DLS sensitivity and require different localization techniques. Laser Voltage Imaging (LVI) and Laser Voltage Probing (LVP) are widely established for logic EFA, [3] but require periodic activation via ATE which may not be possible using MBIST hardware and test-patterns optimized for fast production testing. This paper discusses the test setup challenges to enable LVI & LVP on SRAM fails and includes two case studies on <14 nm advanced process silicon.

In the case of conventional planar FET, Dynamic Laser Stimulation (DLS) is a very effective method to isolate marginal failure. Depending on laser sources, DLS is divided by Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). SDL uses 1320nm wavelength laser source in order to induce localized heat. On the other hand, LADA uses 1064nm wavelength laser source to generate photo carriers. But for the FinFET the effect of laser stimulation is not clear yet. This paper introduces the effect of laser stimulation on FinFET transistors based on wavelength, the so called LADA and two-photon LADA. The experimental data show changes in Vth and Idsat with different character for a single FinFET transistor. A case study further explains this laser stimulation effect via scan chain LVcc marginal failure analysis localized with 1320nm CW laser stimulation and nano-probing analysis.

Dynamic Laser Stimulation (DLS) techniques proved to be very efficient in soft defect localization bringing a lot of information about the device internal behavior. We need to use external parameter measurements such as frequency, delay, voltage etc to perform these techniques. So they can't be used to study internal signal propagation problems in latched device since signals are resynchronized. We will show that we can use the power analysis coupled with DLS techniques set up to characterize soft defect when we don't have a direct access to monitored signal propagation such as in some transistor transition issues. Laser stimulation in addition of power analysis is used to decrypt security codes in security chip, but in failure analysis it is a new way to reach internal information in order to localize soft defects.

A key point to guarantee electronic device quality is device qualification. This part of the process is a significant contributor to the time and cost of the development and production of any electronic device. A device is required to perform a task and its operational lifetime is a key issue for the end user. The more sensitive the qualification technique is, the faster marginalities in the device parameters could be observed. Dynamic Laser Stimulation techniques fill this requirement and could be used in conjunction with traditional qualification procedures.

In the NAND flash manufacturing process, thousands of internal electronic fuses (eFuse) are tuned in order to optimize performance and validity. In this paper, we propose a machine learning optimization technique that uses deep learning (DL) and genetic algorithms (GA) to automatically tune eFuse values. Using state-of-the-art triple-level cell (TLC) V-NAND flash wafers, we trained our model and validated its effectiveness. Based on the findings of the evaluation and production data, the proposed optimization technique can reduce total turnaround time (TAT) by 70% compared with manual eFuse tuning.

Critical speed path analysis using Dynamic Laser Stimulation (DLS) technique has been an indispensable technology used in the Semiconductor IC industry for identifying process defects, design and layout issues that limit product speed performance. Primarily by injecting heat or injecting photocurrent in the active diffusion of the transistors, the laser either slows down or speeds up the switching speed of transistors, thereby affecting the overall speed performance of the chip and revealing the speed limiting/enhancing circuits. However, recently on Qualcomm Technologies’ 14nm FinFET technology SOC product, the 1340nm laser’s heating characteristic revealed a Vt (threshold voltage) improvement behavior at low operating voltages which helped identify process issues on multiple memory array blocks across multiple cores failing for MBIST (Memory Built-in Self-test). In this paper, we explore the innovative approach of using the laser to study Vt shifts in transistors due to process issues. We also study the laser silicon interactions through scanning the 1340nm thermal laser on silicon and observing frequency shifts in a high-speed Ring Oscillator (RO) on 16nm FinFET technology. This revealed the normal and reverse Temperature Dependency Gate voltages for 16nm FinFET, thereby illustrating the dual nature of stimulation (reducing mobility and improving Vt) from a thermal laser. Frequency mapping through Laser Voltage Imaging (LVI) was performed on the Ring Oscillator (RO) using the 1340nm thermal laser, while concurrently stimulating the transistors of the RO. Spatial distribution of stimulation was studied by observing the frequency changes on LVI.

This paper presents the success story of the learning process by reporting four cases using four different failure analysis techniques. The cases covered are IDDQ leakage, power short, scan chain hard failure, and register soft failure. Hardware involved in the cases discussed are Meridian WS-DP, a wafer-level electrical failure analysis (EFA) system from DCG Systems, V9300 tester from Advantest, and a custom cable interface integrating WSDP and V9300 with the adaption of direct-probe platform that is widely deployed for SoC CP test. Four debug cases are reported in which various EFA techniques are proven powerful and effective, including photon emission, OBIRCH, Thermal Frequency Imaging, LVI, LVP, and dynamic laser stimulation.

In this paper we report on the application field of Dynamic Laser Stimulation (DLS) techniques to Integrated Circuit (IC) analysis. The effects of thermal and photoelectric laser stimulation on ICs are presented. Implementations, practical considerations and applications are presented for techniques based on functional tests like Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). A new methodology, Delay Variation Mapping (DVM), will also be presented and discussed.

Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.

Near-infrared laser stimulation techniques such as OBIRCH, TIVA, OBIC and LIVA are now commonly used to localize resistive defects from the front and backside of ICs. However, these laser stimulation techniques cannot be applied to dynamically failed ICs. Recently, two laser stimulation techniques dedicated to dynamic IC diagnostics have been proposed. These two techniques, called Resistive Interconnection Localization (RIL) and Soft Defect Localization (SDL), combine a continuous laser beam with a dynamically emulated IC. The laser stimulation effect on the circuit is monitored through the applied test pattern pass/fail status. This paper presents the methodology to move from static to dynamic laser stimulation. The application of such Dynamic Laser Stimulation (DLS) techniques is illustrated on dynamically failed microcontrollers.

This paper discusses the physics, definitions, and nanoprobing flow of a flash bit memory. In addition, a case study showing the effectiveness of nanoprobing in detecting the Single Bit Fail Data Gain and Data Loss in Flash Memory is also discussed. The paper also includes cases where no passive voltage contrast was observed at the SEM and no leakage was observed at AFM, yet the units failing SBF DG, SBF DL and depletion, were detected by nanoprobing of the single bit. The major finding of this paper is a way to resolve data gain, data loss, and depletion failures of flash memory by nanoprobing procedure, despite no PVC seen at the SEM and no leakage seen at the AFM.

The failure localization on analog & mixed mode ICs in functional mode (AC signals) has become more and more challenging in the last few years. Due to an increasing integration and complexity of these devices, the number of defects, especially those named “soft”, raised considerably. The classical Dynamic Laser Stimulation (DLS) techniques showed some limitations when applied to analog & mixedmode ICs. The SDL (Soft Defect Localization) technique [1] based on binary output signal allows us to localize only the most sensitive areas. The defect in this type of circuits, which are very sensitive to the laser beam [2], is often characterized by a weaker sensitivity than that of “healthy” regions. Hence, xVM (Variation Mapping) techniques were introduced to map some parameters in an analog way (the different sensitivity levels are visualized). To date, the T-LSIM technique [3], the Delay and the Phase Variation Mapping techniques were published [4, 5]. We have already had some interesting results by using these techniques [6] but not every “soft” defect case study could be resolved in that way. In this paper we propose to look at some different parameters which characterize an analog signal and can be used as an input for laser mapping. By applying a simple setup, without any additional sophisticated tool, we show on a “golden” commercial IC the added value of this analysis. We also deal with amplifying the weak signal variations induced by the laser beam scan which often are hidden by the high signal variations in analog or mixed-mode ICs.