Understanding solder joints is very important for failure analysis in semiconductor manufacturing because it is commonly used for mounting semiconductor devices on boards. However, regarding sample preparation for analysis, solder poses challenges in crosssection preparation due to the differences in melting point and hardness of its constituents. Therefore, precision cutting methods such as ion milling are required. On the other hand, ion milling method usually causes thermal damage during cutting. In this paper, we tried to optimize the sample temperature during Ar ion milling using liquid nitrogen cooling [1].

Coating of the Cu bond wire with Pd has been a rather widely accepted method in semiconductor packaging to improve the wire bonding reliability. Based on comparison of a Cu bond wire and a Pd-coated Cu bond wire on AlCu pads that had passed HAST, new insight into the mechanism of the reliability improvement is gained. Our analysis showed the dominant Cu-rich intermetallics (IMC) were Cu3Al2 for the Cu wire, and (CuPdx)Al for the Pd-coated wire. The results have verified the Cu-rich IMC being suppressed by the Pd-coating, which has been extensively reported in literature. Binary phase diagrams of Al, Cu, and Pd indicate that the addition of Pd elevates the melting point and bond strength of (CuPdx)Al compared with CuAl that formed with the bare Cu wire. The improvements are expected to decrease the kinetics of phase transformation toward the more Cu-rich IMC. With the suppression of the Cu-rich IMC, the corrosion resistance of the wire bonding is enhanced and the wire bonding reliability improved. We find that Ni behaves thermodynamically quite similar to Pd in the ternary system of Cu wire bonding, and therefore possesses the potential to improve the corrosion resistance.

Microstructure and its effect on mechanical behavior of ultrafine interconnects have been studied in this paper using a modeling approach. The microstructure from the processes of solidification, spinodal decomposition, and grain growth in ultrafine interconnects has highlighted its importance. The size, geometry and composition of interconnects as well as the elastic energy can influence microstructure and thus the mechanical behavior. Quantification of microstructure in ultrafine interconnects is a necessary step to establish the linkage between microstructure and reliability.

A scanning electron microscopy (SEM) based nano-probing system is used in this study to clarify nickel silicide phase beyond process window. According to the nano-probing measurement result and the cross-sectional transmission electron microscopy (TEM) images, phenomena of junction leakage along with high resistance and a larger nickel silicide area are observed at failure site at the same time. The type of failure mechanism and in-line process issue caused multiple failure phenomena at failure site will be the major focuses in this paper. Nickel silicide phase transformation from NiSi to NiSi2 is highly suspected by the comparison of sheet resistance and silicon consumption. Consequently, nickel silicide beyond process window could be verified immediately.

This paper discusses the issues of tin whisker growth on discrete electronic components. It presents both a critical analysis of existing published documents on tin whisker nucleation and growth and a summary of very recent experiments that provide further understanding of the potential means of whisker formation mitigation. Many of the proposed techniques for reducing the likelihood of whisker formation are inadequate, including control of the immediate underplating material, use of conformal coating, regulating the thickness of the tin coating, use of matte tin electroplating, and annealing or fusing of the tin layer. They likely reduce the incidence of nucleation or growth but do not provide guaranteed protection from lack of whisker formation. The first report of tin whiskers on electronic components dates back to 1946 [16]. Since that time whisker-related problems have been reported consistently. Today the concern is for the of increased number of whisker-related problems due to circuit geometry reductions, lower application voltages and the probability of more suppliers (rapidly) introducing pure tin plated alternatives to comply with pending Pb-free legislation.

A time delayed dielectric breakdown in printed circuit boards, operating at temperatures below the epoxy resin insulation thermo-electrical limits, is reported. The safe temperature-voltage operating regime was estimated and related to the glass-rubber transition (To) of printed circuit board dielectric. The TG was measured using DSC and compared with that determined from electrical conductivity of the laminate in the glassy and rubbery state. A failure model was developed and fitted to the experimental data matching a localized thermal degradation of the dielectric and time dependency. The model is based on localized heating of an insulation resistance defect that under certain voltage bias can exceed the TG, thus, initiating thermal degradation of the resin. The model agrees well with the experimental data and indicates that the failure rate and truncation time beyond which the probability of failure becomes insignificant, decreases with increasing glass-rubber transition temperature.