The goal of this work was to automate the crack detection of pads on a wafer piece. This process allows the engineer to check a huge number of pads for cracks to obtain a meaningful statistical result of the Pad-Over-Active-Areas (POAA) stability, which is a typical task in the failure analysis laboratories. It is possible that cracks in POAA appear during the electrical test or the bonding process. The current analysis process is very time consuming as thousands of pads have to be inspected for cracks by an engineer. The process starts with the chemical preparation of a wafer piece to make the crack below the pad visible. After that, the engineer examines each pad individually through the optical microscope for cracks. For the automation of this process a new workflow had to be developed and is described in this work. Moreover, it comprises the automation of a light microscope as well as an automated image evaluation based on a neural network.

Traditional approaches to navigation in focused ion beam (FIB) circuit edit include blind CAD navigation based on GDSII data from the manufacturer and navigation assisted by the in-situ optical microscope (OM). These approaches are difficult to apply in security audit and reverse engineering fields, where CAD data are unavailable and objects of interest are either too small, or located in an array that is too dense for imaging by in-situ OM. To address this issue, this article presents a methodology which is based on establishing a chip-specific system of coordinates and determination of precise locations of the objects of interest within the device. The work was performed on a Vectra 986 FIB system from FEI Company and a proprietary system for optical scanning of semiconductor devices. Auxiliary techniques allowing enhancement of navigational accuracy, developed for this application, are equally applicable to the general navigation procedures during generic FIB circuit modification.

This paper will demonstrate a new copper (Cu) electroplating technique [1] for accurately isolating high resistance fault locations with resistance below K-order ohms. This phenomenon is achieved by having different electric field intensity leading to different copper deposition rate on the sample surface. From experiments, the interface between the thicker electroplated and thinner electroplated copper layer on the sample surface accurately indicates the high resistance fault location. Also, Optical Microscope (OM) and Focused Ion Beam (FIB) are used to inspect the localized fault site of the electroplated sample. Furthermore, this technique, Electro-Plating Localization Method (EPLM), can process several samples or the entire wafer at the same time. In addition, this technique can be applied in the fully open cases of test vehicles with logical circuit as voltage contrast localization method.

Bond-pad is an important structure of a microelectronic device because it plays the role of enabling the device to communicate with other external devices. Its integrity directly affects the performance of the microelectronic device. This paper presents our investigation on bond-pad Inter-Metal Dielectric (IMD) crack issue. Our investigation has considered the following factors: top via pattern (sea of vias/without vias) for bond-pad, top metal thickness (8 kÅ /9 kÅ /10 kÅ) and probe overdrive force (30 um/50 um/70 um). The bond-pad IMD cracks were exposed and decorated by chemicals (Aqua Regia and Hydrochloric acid), and inspected by an optical microscope. A scoring system was designed to assess the dependence of the bond-pad IMD crack severity on the above-mentioned factors. The investigation results showed that the IMD crack severity is strongly dependent on the probe overdrive force, top via pattern, and only slightly on top metal thickness.

In this paper, the temperature distributions around interconnect defects due to electromigration are presented. A method to overlay the temperature distribution over the optical microscope image of the physical defect has also been developed. This allows a direct correlation of the temperature distribution and the physical structure of the defect.

The present paper describes a backside F/A technique that identifies power IC devices’ I qcc (quiescent Vcc current) failure mechanisms. Choline hydroxide[1, 2] is used to expose the entire die back, keeping gate oxide intact. The perspective gained from the backside etch allows an analyst to quantitatively observe gate oxide defects as well as Si defects. It is discovered that either one of them can cause the same I qcc failure. More than 60 dice can be prepared on one specimen in 2-3 hrs. Another advantage of this technique over conventional top delayering or precision crosssection process is that no SEM work is necessary, only optical microscope is needed to identify defects with typical size of 0.1 μm.

A failure mode occasionally observed in multilayer ceramic capacitors (MLCC) is degradation of insulation resistance as the capacitor ages under temperature and electrical stress. The dielectric in MLCC can have a heterogeneous appearance when examined by optical microscope or SEM. This makes it difficult to identify features that could explain the root cause of failure or that could be used in devising inspection criteria for lot acceptance. Conventional cross sectioning in an epoxy mount leaves the sample unsuitable for examination in highvacuum equipment such as field emission scanning electron microscopy or Auger Electron Spectroscopy (AES) because epoxy outgasses and badly contaminates the high vacuum system. A novel twostep potting technique for sample preparation and inspection was developed to meet these challenges. This technique enabled us to perform electricallymonitored cross sectioning in combination with thermal inspection (infrared microscopy). Once a shorting site was identified, the sample was easily removed from the epoxy mount, allowing examination of the actual location of the short circuit in the field emission SEM (necessary to avoid sample charging). By precisely identifying the defect site, the chemistry of the defect could then be determined using electron spectroscopy and materials identification techniques [1,2,3].

Cracks and other defects in ceramic materials can be difficult or impossible to examine and photograph due to the extreme lack of contrast. A method for inspecting translucent ceramics using scattered light, also known as vicinal illumination, will be described. This method has been known in the ceramics industry for quite some time, but is not well known in the testing and failure analysis community. Electronics applications include substrates, packages, multilayer capacitors, and thin film resistors. Ceramic materials are used in electronic applications as microcircuit packages and substrates which carry signals and power between microcircuits. Fine cracks in ceramic materials can result in mechanical failures, electrical failures, and loss of hermeticity. Often, fine cracks are difficult or impossible to detect using standard nondestructive inspection techniques such as visual inspection, ultrasonic inspection, or vapor crack detection. Dye penetrant inspection is usually effective, but contaminates the part, which is unacceptable for space flight hardware. One effective nondestructive inspection method of detecting cracks involves examining the way in which light scatters through the ceramic material when viewed with a standard bright field reflected light microscope. This method, termed vicinal illumination, has been used for detecting cracks during failure analyses of several part types, and screening of space flight hardware. The technique has proven effective on several different types of ceramic materials as well. A related method for use with dark field equipment has also been used to successfully locate otherwise invisible cracks.