Modern electronic systems rely on components with nanometer-scale feature sizes in which failure can be initiated by atomic-scale electronic defects. These defects can precipitate dramatic structural changes at much larger length scales, entirely obscuring the origin of such an event. The transmission electron microscope (TEM) is among the few imaging systems for which atomic-resolution imaging is easily accessible, making it a workhorse tool for performing failure analysis on nanoscale systems. When equipped with spectroscopic attachments TEM excels at determining a sample’s structure and composition, but the physical manifestation of defects can often be extremely subtle compared to their effect on electronic structure. Scanning TEM electron beam-induced current (STEM EBIC) imaging generates contrast directly related to electronic structure as a complement the physical information provided by standard TEM techniques. Recent STEM EBIC advances have enabled access to a variety of new types of electronic and thermal contrast at high resolution, including conductivity mapping. Here we discuss the STEM EBIC conductivity contrast mechanism and demonstrate its ability to map electronic transport in both failed and pristine devices.

This paper describes the development and implementation of a TEM-based measurement procedure and shows how it is used to determine the verticality or etching angle of channel holes in V-NAND flash with more than 200 layers of memory cells. Despite the high aspect ratio of the region of interest, the method can resolve offsets down to a few nm. Such precision is critical, as the paper explains, because the radius and thus electrical characteristics of each memory cell is determined by the etching angle.

This paper discusses the development of an automated cell layer counting process for preparing 3D NAND flash memory samples for TEM analysis. In an initial proof-of-concept, several line markings were inscribed on the test device in evenly spaced intervals in order to evaluate its helpfulness for a human operator. A more automated procedure was then developed in which cell layers were counted to a desired target layer starting from a reference layer set by the operator. At that point, the operator could begin preparing the TEM sample.

Fault localization using both dynamic laser stimulation and emission microscopy was used to localize the failing transistors within the failing scan chain latch on multiple samples. Nanoprobing was then performed and the source to drain leakage in N-type FinFETs was identified. After extensive detailed characterization, it was concluded that the N-type dopant signal was likely due to projections from the source/drain regions included in the TEM lamella. Datamining identified the scan chain fail to be occurring uniquely for a specific family of tools used during source/drain implant diffusion activation. This paper discusses the processes involved in yield delta datamining of FinFET and its advantages over failure characterization, fault localization, nanoprobing, and physical failure analysis.

Fan Out - Panel Level Packaging (FO-PLP) has redistribution layers (RDLs) which connect IC to a substrate. And each layer in the RDLs is connected through copper micro-vias. Viarelated defects including via separation are very critical because they can escape from electrical test and be found in the field. So many cleaning methods have been developed to keep the target pad surface free of oxides or organic contamination before forming vias. In this paper, we present a via separation case caused by alkaline cleaning introduced before seed metal deposition for electroplating of copper. We investigated the cause by analyzing the microstructure and chemical composition using a focused ion beam (FIB) and a transmission electron microscope (TEM) equipped with an energy dispersive spectrometer (EDS). Via separation, interestingly occurred at the interface between the seed Ti and the seed Cu not the interface between the seed Ti and the target pad..Cu surface which is known to be weak. We suggest a mechanism that structural imperfections at the outer rim of via bottom and galvanic couple of titanium and copper are involved in the separation of vias. Since two dissimilar metals of Ti and Cu are in direct contact, galvanic corrosion can occur in the presence of alkaline solution and discontinuities in the seed Ti layer. We found that galvanic corrosion in the studied system can be further complicated by the existence of copper oxide and titanium oxide as well as Cu and Ti.

As the new generation of microelectronics is pushed into smaller spaces and the yield production is pushing to lower the unoccupied spaces on chips, the local variation of stress has an influence on the component’s performance. This stress comes mainly from different thermal and mechanical properties of the materials used especially in 3D integrations like through silicon via (TSV) technology [1]. Through finite element simulation [2] the internal strain profile was modelled and based on these findings we devised a simulation model for a large area chunk lift out, to preserve the stress inside the material. Standard preparation method for strain measurement is to use a wafer dicing saw and subsequently focused ion beam (FIB) milling, to create lamellae with a defined geometry, close to the desired TSV. This method requires different equipment and knowledge base to achieve a lamella which is still contaminated by Gallium. Therefor we developed our own method based on an FE model of a large chunk lift out, where only a Xenon Plasma FIB is utilized until the local stress measurement using convergent beam electron diffraction (CBED) is measured in a transmission electron microscope (TEM).

Demarest et al. concluded in their previous report that a ten times improvement in placement accuracy was required to enable automated transmission electron microscopy (TEM) sample preparation, and wafer alignment by GDS coordinates demonstrated a factor of two improvement in comparison to optical or scanning electron microscope based processes. This paper provides an additional update on this project. The study is about a GDS based process developed to simplify the complicated workflow for examining discrete electrical failures. The results of this study indicated that the recipe prototype developed on a test structure had a unique feature that consisted of an approximately 45nm by 200nm Cu line segment. Executing the prototype recipe on a wafer at the same process point fabricated 6 months after the original wafer yielded four identical successful samples of about 30nm sample thickness. This technique can thus be extended to large 2D arrays of small structures.

This paper studies the effects of an electron beam and an ion beam in sample preparation at the borderless bit-line contact (CB) between a transistor and a bit line in a deep trench capacitor DRAM [1] using the Transmission Electron Microscope (TEM) and the Electron Energy Loss Spectroscope (EELS). An abnormal region in the Si substrate was observed using cross-sectional TEM (XTEM) analysis at both the opened and un-opened CB contacts when normal sample preparation procedures were applied. CBED (Convergent Beam Electron Diffraction) in the TEM verifies this region is a structure of amorphous Si. The EELS spectrum shows the relative thickness (t/λ) of the TEM sample at this amorphous region is similar to that of the single crystal Si substrate. Experimental results demonstrated that this region was the result of radiation damage caused by either the ion-beam scan or the ion-beam Pt metal deposition required for sample preparation in the Focused Ion Beam (FIB) system. This radiation damage was not caused by inline wafer processing. However, the radiation damage zone for an un-opened contact is smaller than that for an opened contact. The size of the radiation damage zone increases relative to the time of the ion beam exposure. Using electron-beam scan and electron-beam Pt metal deposition can prevent this radiation damage from occurring.

This paper examines copper-interconnect integrated circuit transmission electron microscope (TEM) sample contamination. It investigates the deterioration of the sample during ion milling and storage and introduces prevention techniques. The paper discusses copper grain agglomeration issues barrier/seed step coverage checking. The high temperature needed for epoxy solidifying was found to be harmful to sidewall coverage checking of seed. Single beam modulation using a glass dummy can efficiently prevent contamination of the area of interest in a TEM sample during ion milling. Adoption of special low-temperature cure epoxy resin can greatly reduce thermal exposure of the sample and prevent severe agglomeration of copper seed on via sidewall. TEM samples containing copper will deteriorate when stored in ordinary driers and sulphur contamination was found at the deteriorated point on the sample. Isolation of the sample from the ambient atmosphere has been verified to be very effective in protecting the TEM sample from deterioration.

In semiconductor failure analysis, there is a demand that after mechanical polishing and scanning electron microcopy (SEM) examination, the failure site needs to be analyzed by transmission electron microscope (TEM) for a detailed examination to find the root cause. In this paper, a fast and practical TEM sample preparation method for TEM examination of specific site identified by cross-section scanning electron microscope (SEM) is demonstrated for further structural analysis.

This paper describes a novel method of sample preparation for Transmission Electron Microscope (TEM) analysis, particularly a technique for photoresist sample preparation for TEM analysis. In the analysis of an ultra large scale integrated (ULSI) circuit, the profile images of a ULSI circuit sample are crucial. In order to identify the tiny features of modern semiconductor devices clearly, TEMs are used because of their high spatial resolution. However, TEM analysis is not available for photoresist material, especially for a patterned photoresist layer, due to the difficulty in specimen preparation and its susceptibility to electron beam damage during TEM analysis. A critical step in preparing this type of TEM specimens is to deposit a conductive layer and a dielectric layer upon the patterned phototresist by a physical vapor deposition process at room temperature first, then followed by a focus ion beam (FIB) process. The exact profile of the patterned photoresist is kept, during specimen preparation and TEM analysis, by this modified method. Precise dimension measurements are then possible.