As semiconductor devices continue to decrease in size and pitch, demands for accurate microstructural analysis have increased to enable downward scaling. Critical dimension (CD) metrology is key to delivering process insights, but at such scales, rigorous metrology analysis providing high precision data may lack desired throughput. CD measurement using the scanning electron microscope (SEM) is a widely used technique, however, to acquire large area SEM images with high precision, multiple image stitching is currently required. In this paper, a new method for precise and efficient metrology analysis is introduced. This study demonstrates that large area imaging with ultra-high pixel resolution can deliver better throughput while maintaining the same level of precision that can be achieved by the traditional method.

As integrated circuit (IC) feature dimensions have shrunk, the need for precise and repeatable sample preparation techniques has increased. In this work, the process of preparation of ultrathin planar-to-cross-section conversion transmission electron microscopy (TEM) samples using a gallium dual-column focused ion beam (FIB)/scanning electron microscope (SEM) system is examined. Sample preparation technique in this paper is aimed at repeatably isolating features in the 5-30 nm range, while limiting common issues such as amorphization, lamella warpage, and the curtain effect (or “curtaining”). This can be achieved through careful selection of FIB parameters including ion beam energy, ion beam current, stage tilt, and deposited protective layer materials and thicknesses, which are all discussed in this work.

An approach to overcome barriers to practical Compressed Sensing (CS) implementation in serial scanning electron microscopes (SEM) or scanning transmission electron microscopes (STEM) is presented which integrates scan generator hardware specifically developed for CS, a novel and generalized CS sparse sampling strategy, and an ultra-fast reconstruction method, to form a complete CS system for 2D or 3D scanning probe microscopy. The system is capable of producing a wide variety of highly random sparse sampling scan patterns with any fractional degree of sparsity from 0- 99.9% while not requiring fast beam blanking. Reconstructing a 2kx2k or 4kx4k image requires ~150-300ms. The ultra-fast reconstruction means it is possible to view a dynamic reduced raster reconstructed image based upon a fractional real-time dose. This CS platform provides a framework to explore a rich environment of use cases in CS electron microscopy that benefit from the combination of faster acquisition and reduced probe interaction.

The direct measurement of the memory state (i.e. bit at “0” or at “1”) on single magnetic tunnel junction (MTJ) in a commercial magnetic random access memory (MRAM) remains challenging. In this paper, we propose a probing approach to investigate the MTJ resistance and by this way determine the memory state. To reach this goal, the MRAM device needs to be prepared to create an electrical access to both sides of the MTJs. The suitable methodology consists in a backside preparation routine that creates a bevel allowing us to access the bottom side of the MTJs through vias and the top side to the bitlines. After that, two approaches are discussed to establish the electrical connection. First described is the nanoprobing technique where the electrical connection is created by two nanometric tips positioned in contact on vias and bitlines thanks to a scanning electron microscope. It is then possible to collect the current flowing through the MTJs and to evaluate the resistance. A resistance around 12 kΩ and 14 kΩ were determined for “0” and “1” bits respectively, which is in agreement with literature. Secondly, these measurements will be compared to those resulting from a near-field probing experiment done in a conductive mode. A resistance around 19 kΩ and 24 kΩ were determined for “0” and “1” bits respectively. The use of both methods allows for a cross-reference between the resistance values and a discussion on the advantages and drawbacks of both probing techniques.

The results of analyses on a commercially available 7 nm SRAM, using an in-situ AFM inside a SEM, are presented. In addition to typical results for conductive AFM, a novel method is described that uses the SEM beam to prepare a region for additional material removal, thus bringing out clearer electrical data. This would be of exceptional value for technology nodes using cobalt as a contact material. Finally, techniques making use of the current from the SEM beam as the source of current during the measurement are described. The technique may have value for well resistance measurements using in-situ structures on live product, a survey of junction health, or the localization of point defects.

This presentation is a pictorial guide to the selection and application of measurement methods for defect localization. The presentation covers passive voltage contrast (PVC), nanoprobing, conductive atomic force microscopy, and photon emission microscopy (PEM). It describes signal types, how the measurements are made, the sensing mechanisms involved, and the output that can be expected.

Complex failure analysis often requires the use of multiple characterization instruments. For example, a defect or failure may be localized using one tool, whereas the subsequent marking, precision targeting, and high-resolution analysis may require completely different instruments. As a result, the analysis workflows require sample and operator coordination between instruments and engineers, which leads to lower throughput and success rates. This paper describes a complete in-situ workflow for comprehensive failure analysis processes on a compound semiconductor using a state-of-the-art FIB/SEM system, incorporating electron channeling contrast imaging (ECCI) and a STEM-in-SEM detector used in unison with an insertable detector positioned underneath the sample to capture transmitted electron condensed beam electron diffraction (CBED) micrographs.

This paper explains how the authors determined the cause of a fast-to-rise failure discovered during scan chain testing of an image sensor. The failed device was mounted on a portable card that facilitates transfer between test platforms in an electro-optical probing (EOP) system. Initial fault localization was conducted through backside PEM, but the results were inconclusive. The part was then analyzed on a digital scan chain tester to check for flaws in the daisy chain of shift registers. Through broken scan chain analysis, the potential cause of the problem (a failing flip-flop) was narrowed down to a few chain links and ultimately pinpointed using EOP fault isolation techniques. The failed device was then deprocessed by parallel lapping and analyzed in a SEM, revealing a broken poly gate as the physical cause of failure.

This paper describes optical and electron beam based fault isolation approaches for short and open defects in nanometer-scale through-silicon via (TSV) interconnects. Short defects are localized by photon emission microscopy (PEM) and optical beam-induced current (OBIC) techniques, and open defects are isolated by active voltage contrast imaging in a scanning electron microscope (SEM). The results are confirmed by transmission electron microscopy (TEM) cross-sectioning.

In this paper, we describe the technique of on-axis transmission Kikuchi diffraction (TKD) in a scanning electron microscope and demonstrate its use in characterizing nanoscale crystal structures and defects in semiconductor materials and devices. We explain how we modified hardware and software to achieve an effective spatial resolution of 2 nm during orientation mapping without decreasing acquisition speed, indexing quality, and other performance parameters. The paper includes illustrations comparing sample-detector geometries for conventional EBSD, TKD, and on-axis TKD. It also presents examples of the types of images that can be obtained using on-axis TKD, including raw crystal orientation maps, diffraction patterns, pattern quality maps, time-resolved orientation maps showing microstructure evolution, and a sparse sample map showing the distribution of quantum dots on an electron transparent support film.

This paper presents a die-level sample preparation technique that uses selective etch chemistry and laser interferometry to expose the entire top metal layer surface for electrical fault isolation. It also describes a novel e-beam based probing technique called StaMPS which is used to isolate logic structure failures through SEM image contrasts. By landing SEM probe tips on exposed metal pads and controlling logic states via an applied bias, different levels of contrast are created highlighting structural failure locations. Die-level sample preparation combined with e-beam fault isolation optimizes turnaround time by delayering die in less than an hour and by locating several types of defects in a single sample.

This presentation is a pictorial guide to the selection and application of measurement methods for defect localization. The presentation covers electron beam absorbed current (EBAC), electron beam induced current (EBIC), passive voltage contrast (PVC), optical and electron beam induced resistance change methods (OBIRCH and EBIRCH), lock-in thermography, photon emission microscopy (PEM), and nanoprobing. It describes how the measurements are made, the sensing mechanisms involved, and the output that can be expected.

In the hardware assurance community, Reverse Engineering (RE) is considered a key tool and asset in ensuring the security and reliability of Integrated Circuits (IC). However, with the introduction of advanced node technologies, the application of RE to ICs is turning into a daunting task. This is amplified by the challenges introduced by the imaging modalities such as the Scanning Electron Microscope (SEM) used in acquiring images of ICs. One such challenge is the lack of understanding of the influence of noise in the imaging modality along with its detrimental effect on the quality of images and the overall time frame required for imaging the IC. In this paper, we characterize some aspects of the noise in the image along with its primary source. Furthermore, we use this understanding to propose a novel texture-based segmentation algorithm for SEM images called LASRE. The proposed approach is unsupervised, model-free, robust to the presence of noise and can be applied to all layers of the IC with consistent results. Finally, the results from a comparison study is reported, and the issues associated with the approach are discussed in detail. The approach consistently achieved over 86% accuracy in segmenting various layers in the IC.

For advanced node semiconductor process development, manufacturing, fault isolation and product failure analysis, nanoprobing is an indispensable technology. As the process technology node scales, transistors and materials used are more susceptible to electron beam damage and changes. As scanning electron microscope (SEM) energy decreases to minimize electron beam damage, imaging resolution degrades. Process scaling has not only affected patterning dimensions and pitch scaling, but also materials utilized in advanced nodes. The material used at the contact level has changed from tungsten (W) to cobalt (Co), in combination with ultra-low K dielectrics. These new materials tend to make sample preparation and probing increasingly more challenging. At advanced nodes with sub-20nm contacts, probe landing accuracy and probe-contact stability are important to maintain good electrical contact throughout measurement time. In this paper, we discuss nanoprobing results from a 7nm SRAM obtained from a commercially available leading edge 7nm SOC.

Gate oxide breakdown has always been a critical reliability issue in Complementary Metal-Oxide-Silicon (CMOS) devices. Pinhole analysis is one of the commonly use failure analysis (FA) technique to analysis Gate oxide breakdown issue. However, in order to have a better understanding of the root cause and mechanism, a defect physically without any damaged or chemical attacked is required by the customer and process/module departments. In other words, it is crucial to have Transmission Electron Microscopy (TEM) analysis at the exact Gate oxide breakdown point. This is because TEM analysis provides details of physical evidence and insights to the root cause of the gate oxide failures. It is challenging to locate the site for TEM analysis in cases when poly gate layout is of a complex structure rather than a single line. In this paper, we developed and demonstrated the use of cross-sectional Scanning Electron Microscope (XSEM) passive voltage contrast (PVC) to isolate the defective leaky Polysilicon (PC) Gate and subsequently prepared TEM lamella in a perpendicular direction from the post-XSEM PVC sample. This technique provides an alternative approach to identify defective leaky polysilicon Gate for subsequent TEM analysis.

We report and demonstrate a new methodology for the localization of dielectric breakdown sites in through-silicon via (TSV) structures. We apply a combination of optical beam induced resistance change (OBIRCH) and mechanical/chemical chip deprocessing techniques to localize nm-sized pinhole breakdown sites in a high aspect ratio 3x50 ìm TSV array. Thanks to the wavelength-selective absorption process in silicon, we can extract valuable defect depth localization info from our laser stimulation measurement. After chip deprocessing we inspect and localize the defect site in the dielectric liner using a scanning electron microscope (SEM). We confirm our results and analysis by cross-sectioning a TSV with a focused-ion beam (FIB).

We report on using the voltage-contrast mechanism of a scanning electron microscope to probe electrical waveforms on FinFET transistors that are located within active integrated circuits. The FinFET devices are accessed from the backside of the integrated circuit, enabling electrical activity on any transistor within a working device to be probed. We demonstrate gigahertz-bandwidth probing at 10-nm resolution using a stroboscopic pulsed electron source.

On mechanically polished cross-sections, getting a surface adequate for high-resolution imaging is sometimes beyond the analyst’s ability, due to material smearing, chipping, polishing media chemical attack, etc.. A method has been developed to enable the focused ion beam (FIB) to re-face the section block and achieve a surface that can be imaged at high resolution in the scanning electron microscope (SEM).

Reverse engineering of today’s integrated circuits requires proper sample preparation, high speed imaging and data processing capabilities. The electron-optical design and the data handling architecture of our multi-beam scanning electron microscopes are scalable over a large range of beam numbers, providing sufficient imaging speed - also for the foreseeable future. A first step in data processing for reverse engineering on images acquired with a multi-beam scanning electron microscope has been successfully shown in preliminary tests.

Voltage contrast (VC) observation using a scanning electron microscope (SEM) or a focused ion beam (FIB) is a common failure analysis technique for semiconductor devices.[1] The VC information allows understanding of failure localization issues. In general, VC images are acquired using secondary electrons (SEs) from a sample surface at an acceleration voltage of 0.8–2.0 kV in SEM. In this study, we aimed to find an optimized electron energy range for VC acquisition using Auger electron spectroscopy (AES) for quantitative understanding.