Power MOSFETs are electronic devices that are commonly used as switches or amplifiers in power electronics applications such as motor control, audio amplifiers, power supplies and illumination systems. During the fabrication process, impurities such as copper can become incorporated into the device structure, giving rise to defects in crystal lattice and creating localized areas of high resistance or conductivity. In this work we present a multiscale and multimodal correlative microscopy workflow for the characterization of copper inclusions found in the epitaxial layer in power MOSFETs combining Light Microscopy (LM), non-destructive 3D X-ray Microscopy (XRM), Focused-Ion Beam Scanning Electron Microscopy (FIB-SEM) tomography coupled with Energy Dispersive X-ray Spectroscopy (EDX), and Transmission Electron Microscopy (TEM) coupled with Electron Energy Loss Spectroscopy (EELS). Thanks to this approach of correlating 2D and 3D morphological insights with chemical information, a comprehensive and multiscale understanding of copper segregations distribution and effects at the structural level of the power MOSFETs can be achieved.

Root cause failure analysis of lithium-ion batteries provides important feedback for cell design, manufacture, and use. As batteries are being produced with larger form factors and higher energy densities, failure analysis techniques must be adapted to characteristics of the specific batteries. This paper will discuss the significance of melted copper in lithium-ion battery cells that have experienced thermal runaway and how the interpretation of such evidence has evolved over time. Specialized testing techniques that may prove helpful in determining the root cause of battery failures will also be described.

This paper presents the results of an investigation to gain a better understanding of the impact of wafer substrate copper (Cu) contamination on FinFET devices. A chip from a wafer free of Cu contamination and several chips near a Cu contaminated wafer edge were sampled for chemical, structural, and morphological analysis and electrical device performance testing. The contaminated wafer was also annealed at high temperature, trying to drive Cu diffusion further into the Si substrate. TEM analysis revealed that the Cu interacted with Si to form a stable η-Cu 3 Si intermetallic compound. SIMS analysis from the backside of the wafer detected no Cu even after most of the backside material was removed. Likewise, electrical nanoprobing showed no parametric drift in the FinFETs near the edge of the wafer, comparable to device behavior in a Cu-free Si substrate. These results indicate that the formation of η-Cu 3 Si with a well-defined crystalline structure and stable stoichiometry immobilizes Cu diffusion in the Si substrate. In other words, the impact of Cu diffusion in silicon has no effect on device performance as long as η-Cu 3 Si does not form in the FinFET channel or short any structures within the chip.

In semiconductor manufacturing technology, copper has been widely used for BEOL process due to better conductivity than aluminum. TEM (Transmission Electron Microscopy) characterization has been played in key role to understand the process of semiconductor manufacturing. Gallium base Focused Ion Beam (FIB) is widely used on TEM sample preparation. The experiment to understand the impact of gallium which is from sample preparation process on Cu layer was performed. In-situ TEM studies have shown real time material characteristic of Cu at various temperature [1]. We observed the gallium aggregation phenomenon on Cu layer at round the temperature of 400°C. This thermal aggregation of gallium on Cu layer has been confirmed by EDS analysis in the study. Detectable amount of gallium was found in whole area in the sample before heating the sample at in-situ TEM work. This paper also introduces alternative solutions to resolve this gallium aggregation in copper layer including the sample preparation technique using Xe Plasma Focused Ion Beam (PFIB) [2]. This Xe PFIB showed the substantial improvement of specimen quality for the in-situ TEM experiment of sample preparation.

The development of a characterization workflow for reliable pore characterization of porous metals especially for microelectronics applications is very important. This will help to provide design guidelines for the production and for the improved reliability of the devices. In this paper, we set up a workflow to accurately evaluate the porosity, of four different porous copper materials. The porous thin films are fabricated by using stencil printing. Within the workflow we use for the measurement non-destructive micro-X-ray computed tomography (ƒÝ-XCT) and destructive high-resolution scanning electron focused ion beam nano-tomography (nano-FIB tomography). The latter will be also used to calibrate the threshold for the ƒÝ-XCT image data, since a direct evaluation of the porosity from the non-destructively obtained ƒÝ-XCT image data due to resolution and contrast is not possible. Therefore, we develop an indirect histogram based evaluation method to get the porosity of the porous copper thin films. We validate and discuss the obtained results with respect to further studies.

Today, copper pillar bumping now in high volume production for mobile electronics is also a transformative technology for next generation flip chip [1] interconnects which offers advantages in many designs while meeting current and future requirements. With the continuous shrinking dimensions of semiconductor devices, the package’s design and size are approaching the dimensions of the singulated die. Moreover, failure analysis involving copper pillar packages would be the major challenges faced by analysts as copper pillar devices in nature hides its solder joints beneath its die causing obstruction in quality inspection as well as judging its solder joint strength. Chemical wet etch or deprocessing [2] by using potassium hydroxide (KOH) to remove all silicon die have disadvantages of over etching on silicon substrate and tin (Sn) surrounding the Cu pillar. Therefore, quality of sample preparation is critical and new methodology is needed.

3D integration takes more and more importance in the microelectronics industry. This paper focuses on two types or objects, which are copper pillars (25 micrometer of diameter) and hybrid bonding samples. It aims at a statistical morphology observation of hybrid bonding structures, which underwent an electromigration test at 350 deg C and 20 mA. The goal of the study is two-fold. It is both to limit the overall time needed to perform a whole process flow, from sample preparation to reconstructed volume, and to limit the time of human intervention. To achieve this goal, three strategies are presented: improving the sample preparation scheme, reducing the number of projections with iterative algorithms and the Structural SIMilarity function, and automating the post-processing. The post-processing of the data is fully automated and directly renders the reconstructed volume. The high signal to noise ratio allows for further segmentation and analysis.

Tremendous research efforts have been devoted particularly to the development and improvement of through silicon vias (TSV) in order to provide a key enabling technology for vertical system integration. To achieve high processing yield and reliability efficient failure analysis techniques for process control and root cause analysis are required. The current paper presents an advanced approach for non-destructive localization of TSV sidewall defects applying high resolution Lock-in Thermography and Photoemission Microscopy imaging and defocusing series.

Manufacturing of integrated circuits (ICs) using a split foundry process expands design space in IC fabrication by employing unique capabilities of multiple foundries and provides added security for IC designers [1]. Defect localization and root cause analysis is critical to failure identification and implementation of corrective actions. In addition to split-foundry fabrication, the device addressed in this publication is comprised of 8 metal layers, aluminum test pads, and tungsten thru-silicon vias (TSVs) making the circuit area > 68% metal. This manuscript addresses the failure analysis efforts involved in root cause analysis, failure analysis findings, and the corrective actions implemented to eliminate these failure mechanisms from occurring in future product.

Copper pillar WLCSP device embedded in large PCB module with passive devices to create one hybrid package are growing widely in smart communication and mobile electronic devices. The crucial challenges in electrical testing and failure analysis on it are to remove the embedded copper pillar CSP device from the module without inducing mechanical defects, and solder ball placement on the CSP for ATE testing. This paper discusses the sample preparation process step-by-step, which includes de-soldering of external components from the PCB, top side up and down parallel polishing to remove copper pillars, chemical etching the PCB module, solder ball placement on CSP devices and the soldering process on a plain coupon board. The established process enables electrical testing, evaluations and failure analysis performed on a demounted CSP device. A simulation of an electrical testing and failure analysis will also be highlighted in this paper.

This paper outlines the physical analysis approach to investigate droplet-like copper discoloration defects. These defects are proven to be caused by differences in copper oxidation based on quantification results of the CuO and Cu2O chemical states using X-ray photoelectron spectroscopy (XPS) analysis.

Coating of the Cu bond wire with Pd has been a rather widely accepted method in semiconductor packaging to improve the wire bonding reliability. Based on comparison of a Cu bond wire and a Pd-coated Cu bond wire on AlCu pads that had passed HAST, new insight into the mechanism of the reliability improvement is gained. Our analysis showed the dominant Cu-rich intermetallics (IMC) were Cu3Al2 for the Cu wire, and (CuPdx)Al for the Pd-coated wire. The results have verified the Cu-rich IMC being suppressed by the Pd-coating, which has been extensively reported in literature. Binary phase diagrams of Al, Cu, and Pd indicate that the addition of Pd elevates the melting point and bond strength of (CuPdx)Al compared with CuAl that formed with the bare Cu wire. The improvements are expected to decrease the kinetics of phase transformation toward the more Cu-rich IMC. With the suppression of the Cu-rich IMC, the corrosion resistance of the wire bonding is enhanced and the wire bonding reliability improved. We find that Ni behaves thermodynamically quite similar to Pd in the ternary system of Cu wire bonding, and therefore possesses the potential to improve the corrosion resistance.

Presence of foreign materials (i.e, contamination) can affect the reliability of copper (Cu) bumps when it affects the wettability of the solder and consequently weakens the joint formation of the copper to the substrate. This paper looks at a case of non-wetting of Cu bumps due to silicon contamination induced during assembly processing. In this case study, surface roughness is the main factor being altered when foreign materials contaminate the metal substrate. Sample devices were tested in a resistive open unit and a direct current failing unit, respectively. It was found that the silicon dust present on the substrate in effect "roughens" the surface, thereby decreasing the wettability between the molten solder to the metal substrate. For future studies, it is recommended that the effect of reliability stress activities on the Cu bumps with silicon contaminations be examined to evaluate the risks for possible field failures of this defect.

This paper discusses the application of two different techniques for failure analysis of Cu through-silicon vias (TSVs), used in 3D stacked-IC technology. The first technique is GHz Scanning Acoustic Microscopy (GHz- SAM), which not only allows detection of defects like voids, cracks and delamination, but also the visualization of Rayleigh waves. GHz-SAM can provide information on voids, delamination and possibly stress near the TSVs. The second is a reflection-based photoelastic technique (SIREX), which is shown to be very sensitive to stress anisotropy in the Si near TSVs and as such also to any defect affecting this stress, such as delamination and large voids.

In the authors' previous papers, the failure mechanism and elimination solutions of galvanic corrosion (Al-Cu cell) on microchip Al bondpads in the Al process (0.18un and above) have been studied [1-2]. In this paper, the authors will further study the failure mechanism and root cause of galvanic corrosion (Al-Cu cell) on microchip Al bondpads in the Cu process (0.13um and below) with Ta barrier metal. Based on our results, the root cause of galvanic corrosion (Al-Cu cell) in the Al process is only one way and Al-Cu cell is from Al alloy (Al + 0.5%Cu) on Al bondpads. However, in the Cu process it may be from two ways and Al-Cu cell can be from both Al alloy (Al + 0.5%Cu) on Al bondpads and the Cu metal layer below the barrier metal Ta when Ta has weak points or pinhole. As such, the pinhole defects on Al bondpad caused by galvanic corrosion (Al-Cu cell) in the Cu process might be more serious than that in the Al process. In this paper, TEM is used for root cause identification. Based on the TEM results, galvanic corrosion was due to the weak point/pinhole at the Ta barrier metal layer and Al-Cu diffusion.

Cu wires were bonded to AlSi (1%) pads, subsequently encapsulated and subjected to uHAST (un-biased Highly Accelerated Stress Test, 130 °C and 85% relative humidity). After the test, a pair of bonding interfaces associated with a failing contact resistance and a passing contact resistance were analyzed and compared, with transmission electron microscopy (TEM), electron diffraction, and energy-dispersive spectroscopy (EDS). The data suggested the corrosion rates were higher for the more Cu-rich Cu-Al intermetallics (IMC) in the failing sample. The corrosion was investigated with factors including electromotive force (EMF), self-passivation of Al, thickness and homogeneity of the Al-oxide on the IMC, ratio of the Cu-to-Al surface areas exposed to the electrolyte for an IMC taken into account. The preferential corrosion observed for the Cu-rich IMC is attributed to the high ratios of the surface areas of the cathode and anode that were exposed to the electrolyte, and the passivation oxide of Al with the lower homogeneity. The corrosion of the Cu-Al IMC is just a manifestation of the well-known phenomenon of dealloying. With the understanding of the corrosion mechanisms, prohibiting the formation of Cu-rich IMCs is expected be an approach to improve the corrosion resistance of the wire bonding.

The Aerospace and Defense (A&D) markets are starting to use plastic packages more significantly for Space and Military ruggedized applications. But plastic packages are also inherently less reliable than ceramic devices for A&D applications. The key to the successful use of plastic devices in A&D application is to qualify the devices for the intended application using industry accepted plastic encapsulated microcircuit (PEM) qualification techniques. This paper briefly recaps the test techniques known to be effective in assessing plastic part reliability. But more importantly, it presents actual PEM qualification data gathered over the last 15 years involving over 400 individual PEM Qual lots. The paper also shows the failures modes associated with plastic packages and Cu bond wires. SEM, X-Ray, and Acoustic Microscope images were obtained for the failure modes associated with plastic packages and Cu bond wire.

With the introduction of new packaging technologies and the great variety of semiconductor devices, new decapsulation tools are needed to improve failure analysis with a higher success rate, and to improve quality control with a higher confidence level. Conventional downstream microwave plasma etchers use CF4 or other fluorine containing compounds in the plasma gas that causes unwanted overetching damage to Si3N4 passivation and the Si die, thus limiting its use in IC package decapsulation. The approach of atmospheric pressure O2-only Microwave Induced Plasma (MIP) successfully solves the fluorine overetching problem. Comparison between MIP, conventional plasma, acid etching based on several challenging decapsulation applications has shown the great advantage of MIP in preserving the original status of the die, wire bonds, and failure sites. One of the challenging failure analysis cases is Bond-Over-Active-Circuit (BOAC) devices with exposed thin copper metallization traces on top of Si3N4 passivation. The BOAC critical die structures present a challenge to both conventional plasma and acid decapsulation. The use of MIP to solve the BOAC device decapsulation problem will be discussed in detail through multiple case studies. It appears that the MIP machine is the only approach to decapsulate BOAC devices without causing any damage to the exposed copper on passivation critical structure, which demonstrates the failure analysis capabilities of the MIP system.

Although pre-laser decapsulation reduces the time to acid exposure for subsequent chemical decapsulation of copper wirebonded devices, it can result in severely damaged or broken copper wirebonds if carried out at a focused depth followed by chemical decapsulation. Thin quad flat packages (TQFPs) of dimensions 22 mm × 22 mm, with copper wirebonds were pre-laser decapped (Nd:YAG laser, 1064 nm) at three depths of focus, at focus, (z-0.5) mm and (z-1) mm. Reducing the laser focus depth by 1 mm, followed by subsequent chemical decapsulation, resulted in the least damage to copper wirebonds. Average percentage reduction in copper wirebond diameter after complete (laser and chemical) decapsulation is about 2.30%.

It is well-known that underetch material, contamination, particle, pinholes and corrosion-induced defects on microchip Al bondpads will cause non-stick on pads (NSOP) issues. In this paper, the authors will further study NSOP problem and introduce one more NSOP failure mechanism due to Cu diffusion caused by poor Ta barrier metal. Based on our failure analysis results, the NSOP issue was not due to the assembly process, but due to the wafer fabrication. The failure mechanism might be that the barrier metal Ta was with pinholes, which caused Cu diffused out to the top Al layer, and then formed the “Bump-like” Cu defects and resulted in NSOP on Al bondpads during assembly process.