Metal and dielectric depositions using Xe+ plasma FIB tools are reported and comparisons are made to depositions performed with conventional Ga+ FIB tools. Xe+-deposited Pt had a resistivity of 1250 ± 360 μΩ·cm, similar to the typical range of 1000-2000 μΩ·cm reported for Ga+-deposited Pt. Xe+-deposited dielectric depositions using HMCHS/O2 precursors had an average resistivity of 1.27 x 1019 μΩ·cm (at ± 10V electrical bias), compared to a resistivity of 1.05 x 1014 μΩ·cm for similar Ga+-deposited dielectric films. A comparison between HMCHS/O2 and TMCTS/O2 dielectric depositions was performed for Ga+ systems, and the HMCHS/O2 depositions were found to be orders of magnitude more resistive than the TMCTS/O2 depositions. The experimental difficulties associated with measuring extremely high-resistance films are also briefly discussed.

Sub-nanometer focused inert gas ions derived from a Gas Field Ion Source (GFIS) contain properties that can improve the dimensional and conductivity characteristics of ion beam deposited platinum circuit edit wiring. The following paper, presents ion interaction simulations that help provide insight into the factors which determine the ultimate wire width, resistivity, and metal deposition rates. An experimental result that has aided in the understanding of the primary wire width limiting mechanism is also presented. Finally, a description of the ion beam and precursor properties used for the platinum deposition is provided, a long with a discussion of the wire resistivity measurement technique and challenges. To conclude, the prospects for GFIS ion induced dielectric and metal deposition for circuit edit and nanofabrication applications are discussed.

Electron beam induced radiation damage presents great challenges for the electron microscopy analysis of low k and ultra low k dielectrics due to their beam sensitive nature. In order to minimize the radiation damage, it is necessary to understand the mechanisms behind the damage. This work presents detailed studies regarding the mechanisms behind the effects of probe currents, accelerating voltage and anticharging coating layers on the radiation damage to low/ultralow K dielectrics. The results indicate that the probe current shows a stronger dependence on the size of the condenser lens aperture than the accelerating voltage. Therefore, in terms of the probe current, the condenser lens aperture plays a decisive role in affecting the radiation damage process. In order to minimize the radiation damage, SEM imaging should be conducted with not only a low accelerating voltage but also a small condenser lens aperture to reduce probe current. Based on simulation results, the effects of a coating layer and accelerating voltage are related to the interaction volume and the penetration depth of the electron beam. Pt coating can act as not only an anti-charging layer, but also an effective barrier layer for reducing electron flux that interacts with the low/ultra-low dielectrics.

Electron beam assisted platinum film deposition has been found to be an effective method to protect the sample surface for both FIB and TEM analysis. In this paper, the phenomena of electron beam assisted deposition of platinum will be reviewed The results suggest that a 45 nm thick residual Pt film can effectively protects (100) silicon from damage induced by ion beam assisted Pt deposition. A carbon based organic layer under the electron beam assisted Pt has been observed. The mechanism and results on exposed oxide thickness measurements will be discussed. It is suggested that a carbon glue cap be used as a protective layer or polysilicon be deposited in line before submitting the wafer for TEM sample preparation and observation.

Poly/metal stacked capacitors present challenges in terms of capacitor access and defect localization. As for defect localization, liquid crystal or thermal localization (also OBIRCH/TIVA) and passive voltage contrast (PVC) are used. PVC was found to be effective in terms of finding the bad stacked capacitor and a bad capacitor within the stack. This paper highlights brief process steps in 3-layer polysilicon/metal stacked capacitors. It discusses FA on stacked capacitors, providing information on fault isolation and capacitor access. It presents a case study on differentiating defective capacitors which failing due to vertical shorting. Internal probing between the capacitors within a stack allowed the differentiation between capacitor leakage and capacitor-capacitor shorting. For capacitor leakage, the defect can be identified by parallel lapping to remove the upper capacitor plate. For capacitor-capacitor short, if there is no visual defect seen, Pt chemical etch can be applied for PVC inspection.

A new TEM sample preparation technique was developed to meet the increasing demand and fast turn around time requirements in today’s semiconductor industry. The technique uses a FIB to deposit a thin strip of platinum over the desired structure. The strip then serves as a mask during subsequent etching in a reactive ion etcher. During etching, material on both sides of the strip are removed in a single etch process, leaving a thin wall that is transparent to the electron beam in a TEM. The major advantage of this technique is a 30% to 50% reduction in preparation time of multiple TEM samples.

Achieving high yield in manufacturing of the ICs requires optimization of the processes to provide sufficient process margins affording small deviation from the optimal processing conditions without yield loss. This paper demonstrates the optimization of the process for the improved product yield. Substantial yield loss has been observed in the product wafers due to excessive soft current leakage in the guard ring PtSi Schottky diodes [1]. Physical failure analysis has determined that these leakages were related to the presence of dislocations in the active device regions and different platinum silicide rich phases including: Pt12Si5, Pt6Si5, Pt2Si and Pt3Si. The desired phase is PtSi. The root cause of these defects was associated with the rapid thermal annealing (RTA) used to form the guard ring PtSi Schottky diode platinum silicide contact. The usage of the furnace annealing reduced the leakage of the guard ring Schottky diodes by eliminating dislocations and the presence of the platinum rich phases of the silicide. A variety of the failure analysis techniques were successfully employed in this work including: (1) curve tracer analysis of the Schottky diodes I-V characteristics combined with the emission microscopy of the diodes with consecutive deprocessing of the top metal layers for the purpose of avoiding usage of the back side emission microscopy; (2) scanning electron microscopy (SEM) of the Wright etched cross-sections to determine presence of defects in active device regions, (3) transmission electron microscopy imaging and electron diffraction of the diode cross-sections for determination of the nature of the defects and the structure of the phases present; (4) synchrotron x-ray section topography for determination of the some of the dislocations origins.

The reliability of FIB deposited Pt structures is assessed through lifetesting of product die and through stress testing of via-intensive test structures. Data is also presented for Pt resistance monitors collected over a 21 month period aimed at assessing the stability of the FIB deposition process. Two product types were subjected to HTOL and HTSS conditions at 125°C followed by temperature cycling. The test structures were stressed at different combinations of temperature ranging from 100°C to 140°C and with currents up to 5 mA. Neither product type experienced any FIB related failures whereas the test structure saw 70% fallout due to degradation of the Pt material within the vias. Temperature cycling did not precipitate any failures. The Pt resistance monitor data showed that film resistance increases with film thickness indicating the incorporation of organic byproducts from the deposition process.