Many semiconductor products are manufactured with mature technologies involving the uses of aluminum (Al) lines and tungsten (W) vias. High resistances of the vias were sometimes observed only after electrical or thermal stress. A layer of Ti oxide was found on such a via. In the wafer processing, the post W chemical mechanical planarization (WCMP) cleaning left residual W oxide on the W plugs. Ti from the overlaying metal line spontaneously reduced the W oxide, through which Ti oxide formed. Compared with W oxide, the Ti oxide has a larger formation enthalpy, and the valence electrons of Ti are more tightly bound to the O ion cores. As a result, the Ti oxide is more resistive than the W oxide. Consequently, the die functioned well in the first test in the fab, but the via resistance increased significantly after a thermal stress, which led to device failure in the second test. The NH4OH concentration was therefore increased to more effectively remove residual W oxide, which solved the problem. The thermal stress had prevented the latent issue from becoming a more costly field failure.

Through Silicon Via (TSV) Package (PKG) technology that forms a 3D stack with chip to chip or wafer to wafer contact, uses a variety of wet chemicals unlike conventional package technology. Therefore, new kinds of defects related to the wet chemical occur. In this a new failure mode of disappeared Al pad will be presented, a problem came up to disappear Al pad, which served as the fiducial key during the metal residue removal process after forming the TSV PKG front bump, the mechanism of disappearance of Al pad was investigated. Through chemical analysis of process and equipment, we found that Cu etchant (including H3PO4) can damage for Al pad. The process simulation demonstrated that Al pad actually disappeared. Therefore, it confirmed that it needs to be removed through sufficient rinsing time after applying the wet chemical applied to the TSV PKG process. As a result we solved problem through modified equipment and increased rinsing time.

This paper places a strong emphasis on the importance of applying the correct FA approach in physical sample preparation to identify hidden defects that can be easily removed during analysis. A combination of mechanical parallel polishing and chemical etching was used during the sample preparation after electrical fault isolation. Such a combination is both effective and efficient in identifying the single Via punch-through from a sea of Via in MIM structure as well as finding the thin layer of barrier bridging under the Al metal. It serves as a quick way to verify any suspect without time consuming FIB progressive cuts at the hotspot location which sometimes turns out to be an induced spot with a defect located at other site due to the circuitry connection. It would serve as a good reference to wafer fab that encountered such issues.

This paper placed a strong emphasis on the importance of applying Systematic Problem Solving approach, deep dive and use of right/appropriate FA approach/tools that are essentially critical to FA analysts to understand the “real” root cause. A case of low yield with polar failing pattern was seen and matched well with the Al Pad etch E chuck configuration. Customer also reported of passivation crack issue at the solder bumps. All these evidences suggested the root cause was related to wafer fabrication issue. However, it was through a strong “inquisitive” mindset coupled with the essence of such strong problem solving approach that led to uncover the actual root cause. Although customer test condition was not able to be duplicated due to limited information available in foundry industry, a four point probing alternative method was engaged to overcome this limitation. Unlike typical case, the AlOx thickness was comparable for bad and good dies. Further in depth analysis subsequently revealed the higher O content in the AlOx for the bad dies that was the real culprit for the higher bump resistance. This paper highlights the job of FA analyst is not simply finding defect but also plays a catalyst role in root cause/failure mechanism understanding by providing supporting FA evidence (electrically / physically) to Fab. It would serve as a good reference to wafer Fab that encountered such issue.

In wafer fabrication (Fab), Fluorine (F) based gases are used for Al bondpad opening process. Thus, even on a regular Al bondpad, there exists a low level of F contamination. However, the F level has to be controlled at a lower level. If the F level is higher than the control/spec limits, it could cause F-induced corrosion and Al-F defects, resulting in pad discoloration and NSOP problems. In our previous studies [1-5], the theories, characteristics, chemical and physical failure mechanisms and the root causes of the F-induced corrosion and Al-F defects on Al bondpads have been studied. In this paper, we further study F-induced corrosion and propose to establish an Auger monitoring system so as to monitor the F contamination level on Al bondpads in wafer fabrication. Auger monitoring frequency, sample preparation, wafer life, Auger analysis points, control/spec limits and OOC/OOS quality control procedures are also discussed.

Coating of the Cu bond wire with Pd has been a rather widely accepted method in semiconductor packaging to improve the wire bonding reliability. Based on comparison of a Cu bond wire and a Pd-coated Cu bond wire on AlCu pads that had passed HAST, new insight into the mechanism of the reliability improvement is gained. Our analysis showed the dominant Cu-rich intermetallics (IMC) were Cu3Al2 for the Cu wire, and (CuPdx)Al for the Pd-coated wire. The results have verified the Cu-rich IMC being suppressed by the Pd-coating, which has been extensively reported in literature. Binary phase diagrams of Al, Cu, and Pd indicate that the addition of Pd elevates the melting point and bond strength of (CuPdx)Al compared with CuAl that formed with the bare Cu wire. The improvements are expected to decrease the kinetics of phase transformation toward the more Cu-rich IMC. With the suppression of the Cu-rich IMC, the corrosion resistance of the wire bonding is enhanced and the wire bonding reliability improved. We find that Ni behaves thermodynamically quite similar to Pd in the ternary system of Cu wire bonding, and therefore possesses the potential to improve the corrosion resistance.

Recently a phenomenon has been found that shows different corrosion rates over Al bond pad regardless of different densities of Cl, F components on Al bond pads in different products. According to the results of analysis, the products showed different corrosion rates for different etch conditions of the bond pad opening. For the cause analysis, we conducted a cross-sectional profile comparison between two products with Al bond pads. Based on the result of comparison, we discovered that the side wall profile of the Al bond pad is affected by the etch conditions of the bond pad opening. In some severe cases, it was observed that a small void was formed between the side wall and Al bond pad. Under moist conditions, this void provided moisture between Al bond pad and TiN barrier metal that the electricity contacted. Through this study, we could conclude that the moisture in the void between Al bond pad and TiN barrier metal may create a galvanic corrosive condition.

In the authors' previous papers, the failure mechanism and elimination solutions of galvanic corrosion (Al-Cu cell) on microchip Al bondpads in the Al process (0.18un and above) have been studied [1-2]. In this paper, the authors will further study the failure mechanism and root cause of galvanic corrosion (Al-Cu cell) on microchip Al bondpads in the Cu process (0.13um and below) with Ta barrier metal. Based on our results, the root cause of galvanic corrosion (Al-Cu cell) in the Al process is only one way and Al-Cu cell is from Al alloy (Al + 0.5%Cu) on Al bondpads. However, in the Cu process it may be from two ways and Al-Cu cell can be from both Al alloy (Al + 0.5%Cu) on Al bondpads and the Cu metal layer below the barrier metal Ta when Ta has weak points or pinhole. As such, the pinhole defects on Al bondpad caused by galvanic corrosion (Al-Cu cell) in the Cu process might be more serious than that in the Al process. In this paper, TEM is used for root cause identification. Based on the TEM results, galvanic corrosion was due to the weak point/pinhole at the Ta barrier metal layer and Al-Cu diffusion.

In authors’ previous paper, an OSAT [Optical, SEM (Scanning Electron Microscopy), Auger (Auger Electron Spectroscopy) and TEM (Transmission Electron Microscopy)] methodology was developed for qualification of microchip aluminum (Al) bondpads. Using the OSAT methodology, one can qualify microchip Al bondpads. In this paper, we will further study the NSOP (Non-Stick On Pad) problem on microchip Al bondpads. A new qualification methodology, OSSD [(Optical, SEM, and Surface and Depth profiling X-ray Photoelectron Spectroscopy (XPS)] will be proposed, in which XPS surface analysis is used to check the contamination level of fluorine and carbon on bondpad surfaces instead of Auger analysis. XPS depth profiling analysis will also be used to measure Al oxide thickness instead of TEM analysis. By using OSSD, Al bondpads can be qualified with both reduced costs and shortened turnaround times versus OSAT.

Cu wires were bonded to AlSi (1%) pads, subsequently encapsulated and subjected to uHAST (un-biased Highly Accelerated Stress Test, 130 °C and 85% relative humidity). After the test, a pair of bonding interfaces associated with a failing contact resistance and a passing contact resistance were analyzed and compared, with transmission electron microscopy (TEM), electron diffraction, and energy-dispersive spectroscopy (EDS). The data suggested the corrosion rates were higher for the more Cu-rich Cu-Al intermetallics (IMC) in the failing sample. The corrosion was investigated with factors including electromotive force (EMF), self-passivation of Al, thickness and homogeneity of the Al-oxide on the IMC, ratio of the Cu-to-Al surface areas exposed to the electrolyte for an IMC taken into account. The preferential corrosion observed for the Cu-rich IMC is attributed to the high ratios of the surface areas of the cathode and anode that were exposed to the electrolyte, and the passivation oxide of Al with the lower homogeneity. The corrosion of the Cu-Al IMC is just a manifestation of the well-known phenomenon of dealloying. With the understanding of the corrosion mechanisms, prohibiting the formation of Cu-rich IMCs is expected be an approach to improve the corrosion resistance of the wire bonding.

It is well-known that underetch material, contamination, particle, pinholes and corrosion-induced defects on microchip Al bondpads will cause non-stick on pads (NSOP) issues. In this paper, the authors will further study NSOP problem and introduce one more NSOP failure mechanism due to Cu diffusion caused by poor Ta barrier metal. Based on our failure analysis results, the NSOP issue was not due to the assembly process, but due to the wafer fabrication. The failure mechanism might be that the barrier metal Ta was with pinholes, which caused Cu diffused out to the top Al layer, and then formed the “Bump-like” Cu defects and resulted in NSOP on Al bondpads during assembly process.

In wafer fabrication, Fluorine (F) contamination may cause fluorine-induced corrosion and defects on microchip Aluminum (Al) bondpads, resulting in bondpad discoloration or non-stick on pads (NSOP). Auger Electron Spectroscopy (AES) is employed for measurements of the fluorine level on the Al bondpads. From a Process control limit and a specification limit perspective, it is necessary to establish a control limit to enable process monitor reasons. Control limits are typically lower than the specification limits which are related to bondpad quality. The bondpad quality affects the die bondability. This paper proposes a simulation method to determine the specification limit of Fluorine and a Shelf Lifetime Accelerated Test (SLAT) for process monitoring. Wafers with different F levels were selected to perform SLAT with high temperature and high relative humidity tests for a fixed duration to simulate a one year wafer storage condition. The results of these simulation results agree with published values. If the F level on bondpad surfaces was less than 6.0 atomic percent (at%), then no F induced corrosion on the bond pads was observed by AES. Similarly, if the F level on bond pad surfaces was higher than 6.0 atomic per cent (at%) then AES measured F induced corrosion was observed.

Performance degradation due to fatigue accumulation from the repetitive switching of high load current is critical to understanding robust power MOSFET product design. In this paper, we present a novel high-current-temperature (HCT) characterization system used to investigate real world powercycling failure mechanisms. The effects of electric current Joule heating, non-uniform temperature distribution and performance deterioration of discrete power devices are discussed. Thermal fatigue of solder joints and thick aluminum wire bonding are common weak spots with regard to power-cycling capability. We report performance failure mechanisms and discuss the superposition of contributing factors in defining root cause. Results discuss various package influences as part of a robust power MOSFET development process.

This paper presents a quick, reliable, and fully quantitative method of measuring the intermetallic coverage of copper to aluminium bonding at time zero and post reliability stressing. This method is currently used in select manufacturing quality control processes, as well as during product release procedures. By applying this measurement method after various life-tests, it has been possible to collect information on degradation in the copper aluminium system which is currently being used to make a model of the corrosion mechanism in the copper aluminium system.

A case study of Fluorine (F)-outgassing is presented in this paper that caused the corrosion of Aluminum bond pad. It will be shown that the source of F-contamination is not the typical residue left behind after the passivation etch with Fluorine-based gas chemistry and the subsequent removal of the etch polymer generated with solvent (chemical) clean. Rather, it is introduced as a result of F-outgas over a period of time from the intermetallic dielectric (IMD) film, fluorosilicate glass (FSG), during the post-fab wafer storage. The methodology used in our failure analysis (FA) lab to identify and characterize this type of failure mode is presented in the paper.

Cu needs a higher level of ultrasound combined with bonding force to be bonded to the Al pad properly, not just because Cu is harder than Au, but it is also harder to initiate intermetallic compounds (IMC) formation during bonding. This increases the chances of damaging the metal/low k stack under the bondpad. This paper presents a fundamental study of IMC as well as one example of a failure mode of Cu/Al bonded devices, all based on detailed analysis using scanning electron microscopy, scanning transmission electron microscopy, energy dispersive spectrometers, and transmission electron microscopy. It presents a case study showing a corrosion mechanism of Cu/Al ballbond after 168hr UHAST stress. It is observed that all Cu9Al4 was consumed, while very little copper aluminide remained after 168 hours of UHAST stressing.

Fluorine-induced corrosion is one of the well-known failure modes of Al bondpad leading to non-stick on pad (NSOP) issues. Exposure to moisture (H2O) and atmosphere (O2) play an important role in determining the shape and size of the Al-F corrosion defects on the Al bondpad surface. In this paper, we will propose a laboratory simulation methodology that can reproduce F-induced defects observed either at the wafer fab or the assembly house. The methodology, known as SLAT ( S helf L ifetime A cceleration T est), is used to study the relationship between the F-corrosion defects and the relative temperature (T) and humidity (RH %). It is observed that Al-F corrosion defects simulated are similar to the real defects found in wafer fab and assembly house in our previous studies. A relatively higher T and lower RH % results in the formation of the “crystal-like” defects, but if a relatively lower T and higher RH % condition is used, the “oxide-like” defects were formed. In this paper, we will compare the simulation results to the real defects found in the previous cases and discuss the failure mechanism. From the present study, the importance of controlling T and RH % during wafer storage to eliminate F-induced defects will be highlighted.

This paper presents a mechanical cross-sectioning approach that produces an image clarity not yet demonstrated in published literature. It demonstrates how a critical sequence of polishing, basic slurry optimization and staining, in conjunction with correct imaging parameters can be used to highlight the growth morphology of the intermetallic compound (IMCs). Utilizing this approach, the paper describes the results of a SEM imaging study of the intermetallic formation and growth at the Cu-Al bond interface during thermal ageing for up to 4000hrs at 150 deg C. The paper uses direct SEM imaging to catalog observations which are used to create an initial model for IMC and void growth at the wire bonded interface. It examines the effect of aluminum splash and concludes that growth of intermetallics at the Cu-Al interface is rapid into the bond-pad aluminum than into the Cu-ball, but the growth thickness uniformity is much higher into the Cu-ball.

Wire bonding continues to remain as the dominant chip interconnect technology in the far backend process, regardless of the shrinkage of microchip Al bond pad size and the increase in the number of I/O connections in the modern ICs. The reliability of IC devices is directly affected by the quality of adhesion between wire bond and microchip Al pad. Many factors, such as the wafer fab process residue and corrosion, creep-induced wire breakage and electrostatic damage, may result in poor adhesion. In this paper, we show a p-channel Field-Effect Transistor (pFET) failure caused by a mismatch in the bond pad size and the wire bond diameter as well as electrostatic damage during wire bonding. The failure analysis results, failure mechanism and the design rule of microchip Al bond pad in wafer fabrication are discussed. FA investigations were performed on the high gate leakage (nA to mA level) issue in the packaged pFET. It was found that two major factors contributed to the failure, namely mechanical and electrostatic damage. The mechanical damage was mainly due to incompatible Al pad size and bond wire diameter. More specifically, in the failed device, the bond wire diameter was larger than half size of the bond pad opening, contrary to the general design rules of wire bonding. The failure to adhere to the design rule resulted in the device failure. In addition, the electrostatic damage during wire bonding resulted in defects of poly Si/gate oxide and thus the high gate leakage. In this paper, the FA results, failure mechanism of the high gate leakage and the bond pad design rule will be discussed. Also, it will be demonstrated that to achieve good bonding quality and eliminate mechanical and ESD damage the diameter of the bond wire should be equal to or smaller than half of the bond pad opening.

Grain size monitor of Al pad is necessary to assure pad quality and electrical performance in IC manufacturing. Currently, the sample is prepared either without pretreatment or with 4.9% HF stain or ion milling before grain size measurement. In this paper, we demonstrate the pretreatment has a pronounced effect on the grain size measurement and the method with ion milling pretreatment shows more reliable results. The mechanism is further discussed.