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Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 351-357, October 28–November 1, 2024,
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In nanoscience, techniques based on Atomic Force Microscope (AFM) stand as a cornerstone for exploring local electrical, electrochemical and magnetic properties of microelectronic devices at the nanoscale. As AFM's capabilities evolve, so do the challenges of data analysis. With the aim of developing a prediction model for AFM mappings, based on Machine Learning, this work presents a step towards the analysis and benefit of Big Data recorded in the hyperspectral modes: AFM DataCube. The MultiDAT-AFM solution is an advanced 2000-line Python-based tool designed to tackle the complexities of multi-dimensional measurements and analysis. MultiDAT-AFM offers visualization options, from acquired curves to scanned mappings, animated mappings as movies, and a real 3D-cube representation for the hyperspectral DataCube modes. In addition, MultiDAT-AFM incorporates a Machine Learning algorithm to predict mappings of local properties. After evaluating two supervised Machine Learning algorithms (out of the eight tested) for regression, the Random Forest Regressor model emerged as the best performer. With the refinement step, a root mean square error (RMSE) of 0.18, an R 2 value of 0.90 and an execution time of a few minutes were determined. Developed for all AFM DataCube modes, the strategy and demonstration of MultiDAT-AFM are outlined in this article for a silicon integrated microelectronic device dedicated to RF applications and analyzed by DataCube Scanning Spreading Resistance (DCUBE-SSRM).
Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 406-410, October 28–November 1, 2024,
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Integrated circuit (IC) de-processing is a crucial step in failure analysis (FA) for defect validation and root cause identification. The commonly used FA de-processing technique is top-down delayering, this is because of faster and easier for sample preparation. However, backside de-processing is occasionally necessary for fault isolation, better root cause understanding, and formulating the failing mechanism such as gate oxide defects, front-end of line (FEOL) defects, back-end of line (BEOL) vertical shorts, high power Ga-N on Silicon (Si) substrate device, etc. This paper introduces an innovative backside de-processing method for ICs utilizing laser ablation by employing a commercial laser decapsulation system. We thin the backside Si substrate via laser ablation and subsequent chemical etching, revealing FEOL defects. Experimental results demonstrate the method's efficiency, offering enhanced sample handling and reduced preparation time. The proposed backside laser de-processing technique proves to be a superior choice compared to conventional methods in terms of success rate, de-processing speed, and cost-effectiveness. This research contributes to advancing FA methodologies by introducing an innovative approach for backside physical FA applications, opening new possibilities for efficient and accurate IC analysis.
Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 416-421, October 28–November 1, 2024,
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Mechanical sample preparation is a crucial and indispensable step in modern failure analysis (FA). Traditional methods excel in reducing bulk silicon to thicknesses of several tens of micrometers. However, contemporary demands necessitate sample preparation below 10 µm or even below 5 µm, which is challenging, time-consuming, and requires an expensive toolset and advanced operator expertise. Existing methods, which rely on mechanical components for bulk removal, induce mechanical stress and microcracks that can alter the electrical characteristics of the sample. Maintaining the sample's electrical behavior is essential for accurate FA. This paper introduces a novel approach to sample preparation that employs concepts from wafer-level chemical mechanical polishing (CMP). This method ensures reliable sample preparation without introducing microcracks, accurately halts material removal at the shallow trench isolation (STI) – or deep STI - level, and maintains the sample's electrical functionality. The proposed approach is discussed in detail, including successful thinning of various sample types to the STI level, which were subsequently tested for electrical functionality.
Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 509-514, October 28–November 1, 2024,
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III-V power electronic devices are a growing industry as electric vehicles (EVs), power-demanding servers, and other high-power electronics become more prominent. The design of these devices can alter a failure analysis lab’s process flow typically used on traditional silicon-based logic devices. One such obstacle is backside fault isolation (FI) through highly doped silicon wafers used in GaN-on-Si technologies. Backside fault isolation is critical for many electrical failure analyses so finding several approaches to enable this technique that fits current FA flows is desirable. Chemical and Focused Ion Beam (FIB) based approaches have been used to enable backside FI [1], [2]. This paper considers a plasma-based approach with two separate machines, a Microwave Induced Plasma spot etcher and a chamber based Reactive Ion Etch (RIE). Both utilize a Fluorine-based chemistry which is highly selective to the silicon vs the underlying GaN. The etches are used to selective remove the silicon to form a window to the underlying GaN material. Subsequent backside FI analyses are successfully followed by several other analyses.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 164-167, November 12–16, 2023,
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With the introduction of flip-chip technology, optical-based failure analysis techniques have played a critical role in many failure analysis (FA) laboratories. This is due to the unhindered access for photons to probe or emit from the transistor layer through the bulk silicon. Among the optical techniques, laser voltage imaging (LVI) and laser voltage probing (LVP), collectively called LVx, dominate because they directly expose the electrical activity of a given circuit or cell.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 265-270, November 12–16, 2023,
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When aiming for extreme thinning of the bulk silicon down to the shallow trench isolation (STI) level, endpoint determination is a challenging task. Here, we present a novel approach providing reliable access to the STI level of single dies. Therefore, we transfer the wafer-based CMP process to be applicable to single dies on a table-top machine. In a first step, the developed process is applied to the whole IC backside simultaneously. Using a highly selective slurry with a material removal ratio from Si to SiO of more than 500:1 ensures that the STI level remains intact. Two types of samples have been prepared for experiments performed for this paper. A 115mm x 80mm flip-chip bonded device with a bulk silicon thickness of 500μm has been prepared to STI level within less than 4 hours.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 279-281, November 12–16, 2023,
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In this paper, we propose a method to get more accurate metrology data using the tilt-axis on a transmission electron microscope (TEM) to compensate for microscopic tilt-axis changes that occur during focused ion beam (FIB) sample preparation processing. This method was developed using V-NAND plan-view samples which require channel hole measurements for each layer to support process monitoring. To test this method, we obtained the same image by progressively tilting the alpha and beta axes one degree in the positive and negative direction using a V-NAND planar sample. The strongest contrast edge was found by contrast profile analysis of each edge of the V-NAND channel using automated software. Through this method, we were able to optimize the sample position and automate the process to capture high quality images to accurately measure V-NAND channel holes. The details are discussed in this paper.
Proceedings Papers
ISTFA2022, ISTFA 2022: Tutorial Presentations from the 48th International Symposium for Testing and Failure Analysis, d1-d78, October 30–November 3, 2022,
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This presentation provides an overview of photonic measurement techniques and their use in isolating faults and locating defects in ICs. It covers transmission, reflectance, and absorption methods, describing key interactions and important parameters and equations. Reflectance methods discussed include electro-optical probing (EOP), electro-optical frequency modulation (EOFM), and laser-voltage imaging (LVI). Absorption methods covered include those based on the absorption of light in semiconductors, as in optical beam induced current (OBIC), light-induced voltage alteration (LIVA), and laser-assisted device alteration (LADA), and those based on absorption in metals, as in thermally induced voltage alteration (TIVA), optical beam induced resistance change (OBIRCH), and thermoelectric voltage generation or Seebeck effect imaging (SEI). The presentation also covers thermoluminescence (lock-in thermography) and electroluminescence (photon emission) measurement methods and assesses hardware security risks posed by current and emerging photonic localization techniques.
Proceedings Papers
Fast and Effective Sample Preparation Technique for Backside Fault Isolation on GaN Packaged Devices
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 279-282, October 31–November 4, 2021,
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This paper describes a procedure for preparing packaged GaN devices for photon emission microscopy from the backside, which has proven to be an effective method for isolating faults. The deprocessing technique was developed for GaN devices formed on thick p ++ silicon substrates mounted in quad-flat no-lead (QFN) packages connected by gold wires. It consists of mechanical polishing, which removes backside metal and packaging material, and selective etching, which quickly etches the silicon while leaving the gold wires intact for electrical measurements. The authors describe each step of the process in detail and explain how emission spots are marked with a UV laser and analyzed in a FIB-SEM system to determine the underlying cause of failure.
Proceedings Papers
ISTFA2021, ISTFA 2021: Tutorial Presentations from the 47th International Symposium for Testing and Failure Analysis, d1-d96, October 31–November 4, 2021,
Abstract
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This presentation provides an overview of photonic measurement techniques and their use in isolating faults and locating defects in ICs. It covers transmission, reflectance, and absorption methods, describing key interactions and important parameters and equations. Reflectance methods discussed include electro-optical probing (EOP), electro-optical frequency modulation (EOFM), and laser-voltage imaging (LVI). Absorption methods covered include those based on the absorption of light in semiconductors, as in optical beam induced current (OBIC), light-induced voltage alteration (LIVA), and laser-assisted device alteration (LADA), and those based on absorption in metals, as in thermally induced voltage alteration (TIVA), optical beam induced resistance change (OBIRCH), and thermoelectric voltage generation or Seebeck effect imaging (SEI). The presentation also covers thermoluminescence (lock-in thermography) and electroluminescence (photon emission) measurement methods and assesses hardware security risks posed by current and emerging photonic localization techniques.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 79-83, November 15–19, 2020,
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Currently gaps in non-destructive 2D and 3D imaging in PFA for advanced packages and MEMS exist due to lack of resolution to resolve sub-micron defects and the lack of contrast to image defects within the low Z materials. These low Z defects in advanced packages include sidewall delamination between Si die and underfill, bulk cracks in the underfill, in organic substrates, Redistribution Layer, RDL; Si die cracks; voids within the underfill and in the epoxy. Similarly, failure modes in MEMS are often within low Z materials, such as Si and polymers. Many of these are a result of mechanical shock resulting in cracks in structures, packaging fractures, die adhesion issues or particles movements into critical locations. Most of these categories of defects cannot be detected non-destructively by existing techniques such as C-SAM or microCT (micro x-ray computed tomography) and XRM (X-ray microscope). We describe a novel lab-based X-ray Phase contrast and Dark-field/Scattering Contrast system with the potential to resolve these types of defects. This novel X-ray microscopy has spatial resolution of 0.5 um in absorption contrast and with the added capability of Talbot interferometry to resolve failure issues which are related to defects within organic and low Z components.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 129-132, November 15–19, 2020,
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The characterization of Back Side Illumination (BSI) Image Sensor is challenging because of its unique construct with silicon on top. A novel approach for the BSI Image sensor characterization will be presented in this paper. The proposed approach utilizes the circuit editing through the silicon (backside) by ion beam and optical imaging. This technique allows access to the buried conductors and creates probe points for measurements, which are typically performed by an optical prober, electron beam prober or a mechanical micro/nano prober.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 345-351, November 15–19, 2020,
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Scan-based test has been the industrial standard method for screening manufacturing defects. Scan chains are vulnerable to most manufacturing defects and process variations. Therefore, chain failures diagnosis is critical for successful yield learning. However, traditional chain diagnosis requires failing masking patterns to identify faulty chains and their fault types for designs with test compression. In other words, it cannot diagnose the chain failures which don't fail the masking chain patterns. Unfortunately, advanced FinFET technologies with more manufacturing challenges and higher process variations may result in more subtle chain timing failures which can't be detected by chain masking patterns. In this work, we present a new debugging methodology, which combines chain diagnosis and tester-based test to effectively diagnose such intermittent chain failures. The proposed methodology is validated on silicon data for one modern large SOC design and successfully identified all scan cells with hold-time issues, which were validated by STA with corrected models. The subsequent mask fixes for these identified hold-time violations resolved this yield issue and dramatically improve the yield.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 20-24, November 10–14, 2019,
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We report and demonstrate a new methodology for the localization of dielectric breakdown sites in through-silicon via (TSV) structures. We apply a combination of optical beam induced resistance change (OBIRCH) and mechanical/chemical chip deprocessing techniques to localize nm-sized pinhole breakdown sites in a high aspect ratio 3x50 ìm TSV array. Thanks to the wavelength-selective absorption process in silicon, we can extract valuable defect depth localization info from our laser stimulation measurement. After chip deprocessing we inspect and localize the defect site in the dielectric liner using a scanning electron microscope (SEM). We confirm our results and analysis by cross-sectioning a TSV with a focused-ion beam (FIB).
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 99-103, November 10–14, 2019,
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High numerical aperture (NA) laser scanning for fault localization requires the use of special lenses aimed at creating a tightly focused laser spot within an integrated circuit. Typically, extrinsic solid immersion lenses are employed that optimize the refraction at the air-silicon surface. In this feasibility study we investigate with both simulations and experiments the use of integrated diffraction lenses for high-NA imaging. We take the limit to ultrathin silicon and discuss the implications for the lens design and performance.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 179-181, November 10–14, 2019,
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Static Random-Access Memory (SRAM) failure analysis (FA) is important during chip-level reliability evaluation and yield improvement. Single-bit, paired-bit, and quad-bit failures—whose defect should be at the failing bit-cell locations—can be directly sent for Physical Failure Analysis (PFA). For one or multiple row/column failures with too large of a suspected circuit area, more detailed fault isolation is required before PFA. Currently, Photon Emission Microscopy (PEM) is the most commonly used Electrical Failure Analysis (EFA) technique for this kind of fail [1]. Soft-Defect Localization / Dynamic Laser Stimulation (SDL/DLS) can also be applied on soft (Vmin) row/column fails for further isolation [2]. However, some failures do not have abnormal emission spots or DLS sensitivity and require different localization techniques. Laser Voltage Imaging (LVI) and Laser Voltage Probing (LVP) are widely established for logic EFA, [3] but require periodic activation via ATE which may not be possible using MBIST hardware and test-patterns optimized for fast production testing. This paper discusses the test setup challenges to enable LVI & LVP on SRAM fails and includes two case studies on <14 nm advanced process silicon.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 445-453, November 10–14, 2019,
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Backside silicon removal provides an avenue for a number of modern non-destructive and circuit edit techniques. Visible light microscopy, electron beam microscopy, and focused ion beam circuit edit benefit from a removal of back side silicon from the integrated circuit being examined. Backside milling provides a potential path for rapid sample preparation when thinned or ultrathinned samples are required. However, backside milling is an inherently destructive process and can damage the device function, rendering it no longer useful for further nondestructive analysis. Recent methods of backside milling do not guarantee device functionality at a detected end point without a priori knowledge. This work presents a methodology for functional end point detection during backside milling of integrated circuit packaging. This is achieved by monitoring second order effects in response to applied device strain, which guide the milling procedure, avoiding destructive force as the backside material is removed. Experimental data suggest a correlation between device power consumption waveforms and second order effects which inform an in situ functional end point. Keywords: functional end point, side-channel analysis, backside thinning, milling, machine learning, second order effects
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 454-459, November 10–14, 2019,
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Infrared optical probing techniques that have significant applications to and continued development for silicon physical debug have existed for decades. More recently, resolution enhancement achieved by improving numerical aperture, etc. have reached fundamental limits and the ability for resolution to match node scaling with radiation transparent to silicon (photon energy < silicon bandgap) becomes diffraction limited for some 10nm and many future process nodes. Decreasing the wavelength used for imaging and signal acquisition can improve resolution; however, it is well documented that absorption increases sharply for photons with energy greater than the bandgap of the bulk substrate material. Significant reduction in the thickness of the backside substrate material can be performed to achieve acceptable transmission through the absorbing substrate, but the requirement for very thin sample preparation significantly modifies the thermal system surrounding active circuitry. Here, high aspect ratio trenches are shown to offer a unique method to take advantage of thick silicon (> 100µm) for lateral heat dissipation as well as thin silicon (< 2µm) for minimally absorbing optical path in close proximity to enable case-by-case preparation methods for postsilicon labs faced with visible light resolution requirements on high power density circuits.
Proceedings Papers
ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 309-314, October 28–November 1, 2018,
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Low power mode current is a very important parameter of most microcontrollers. A non-production prototype microcontroller had high current issues with certain SRAM modules which were produced using a new memory compiler. All devices were measuring 100’s μA of low power mode current which was an order of magnitude higher than the requirement. Many failure analysis (FA) techniques had to be used to determine the root cause: Optical Beam Induced Resistance Change (OBIRCh), photo emission microscopy (PEM), microprobing, and nanoprobe device characterization. Transistor models and measurements of probe structures from the effected lots both predicted that the device low power mode current would meet expectations; however, all first silicon samples had elevated low power mode current. A knowledge of low power design methodology was needed to ensure all issues were discovered.
Proceedings Papers
ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 363-367, October 28–November 1, 2018,
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As semiconductor devices continue to shrink, novel materials (e.g. (Si)Ge, III/V) are being tested and incorporated to boost device performance. Such materials are difficult to grow on Si wafers without forming crystalline defects due to lattice mismatch. Such defects can decrease or compromise device performance. For this reason, non-destructive, high throughput and reliable analytical techniques are required. In this paper Electron Channeling Contrast Imaging (ECCI), large area mapping and defect detection using deep learning are combined in an analytical workflow for the characterization of the defectivity of “beyond Silicon” materials. Such a workflow addresses the requirements for large areas 10 -4 cm 2 with defect density down to 10 4 cm -2 .
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