This presentation covers the theory and practice of scanning transmission electron microscopy in a scanning electron microscope or STEM-in-SEM. It provides a detailed overview of the measurement physics, the equipment required, the importance of collection angle control, and contrast interpretation. It explains how and why different detectors are used and how they are calibrated. It addresses the issue of beam damage and explains how to quantify and deal with it. It also covers advanced concepts, including 4D STEM-in-SEM, nanoscale strain and temperature mapping, and the use of programmable STEM detectors for imaging and diffraction, and provides examples demonstrating the capabilities of the various measurement setups.

In this paper, we describe the technique of on-axis transmission Kikuchi diffraction (TKD) in a scanning electron microscope and demonstrate its use in characterizing nanoscale crystal structures and defects in semiconductor materials and devices. We explain how we modified hardware and software to achieve an effective spatial resolution of 2 nm during orientation mapping without decreasing acquisition speed, indexing quality, and other performance parameters. The paper includes illustrations comparing sample-detector geometries for conventional EBSD, TKD, and on-axis TKD. It also presents examples of the types of images that can be obtained using on-axis TKD, including raw crystal orientation maps, diffraction patterns, pattern quality maps, time-resolved orientation maps showing microstructure evolution, and a sparse sample map showing the distribution of quantum dots on an electron transparent support film.

This presentation covers the principles of STEM-in-SEM technology and its application in materials research and failure analysis. Part 1 describes the arrangement and function of major components in TEM-in-STEM systems, compares and contrasts imaging modes, and explains how different types of images are obtained by adjusting imaging parameters. Part 2 covers the implementation and use of 4D STEM-in-SEM. It provides examples showing how the method is used to examine diffraction patterns, capture images of materials susceptible to low-energy beam damage, and produce nanoscale strain, grain orientation, and temperature maps. It also includes a wide range of images obtained using a programmable STEM detector.

As the new generation of microelectronics is pushed into smaller spaces and the yield production is pushing to lower the unoccupied spaces on chips, the local variation of stress has an influence on the component’s performance. This stress comes mainly from different thermal and mechanical properties of the materials used especially in 3D integrations like through silicon via (TSV) technology [1]. Through finite element simulation [2] the internal strain profile was modelled and based on these findings we devised a simulation model for a large area chunk lift out, to preserve the stress inside the material. Standard preparation method for strain measurement is to use a wafer dicing saw and subsequently focused ion beam (FIB) milling, to create lamellae with a defined geometry, close to the desired TSV. This method requires different equipment and knowledge base to achieve a lamella which is still contaminated by Gallium. Therefor we developed our own method based on an FE model of a large chunk lift out, where only a Xenon Plasma FIB is utilized until the local stress measurement using convergent beam electron diffraction (CBED) is measured in a transmission electron microscope (TEM).

This paper discusses the Failure Analysis methodology used to characterize 3D bonded wafers during the different stages of optimization of the bonding process. A combination of different state-of-the-art techniques were employed to characterize the 3D patterned and unpatterned bonded wafers. These include Confocal Scanning Acoustic Microscopy (CSAM) to determine the existence of voids, Atomic Force Microscopy (AFM) to determine the roughness of the films on the wafers, and the Double Cantilever Beam Test to determine the interfacial strength. Focused Ion Beam (FIB) was used to determine the alignment offset in the patterns. The interface was characterized by Auger Spectroscopy and the precession electron nanobeam diffraction analysis to understand the Cu grain boundary formation.

The results presented here show how high-speed simultaneous EBSD and EDS can be used to characterize the essential microstructural parameters in SnPb solder joints with high resolution and precision. Analyses of both intact and failed solder joints have been carried out. Regions of strain localization that are not apparent from the Sn and Pb phase distribution are identified in the intact bond, providing key insights into the mechanism of potential bond failure. In addition, EBSD provides a wealth of quantitative detail such as the relationship between parent Sn grain orientations and Pb coarsening, the morphology and distribution of IMCs on a sub-micron scale and accurate grain size information for all phases within the joint. Such analyses enable a better understanding of the microstructural developments leading up to failure, opening up the possibility of improved accelerated thermal cycling (ATC) testing and better quality control.

In this paper, a sample was made on an advanced technology node finFET test structure and analyzed in a 200kV TEM equipped with a 4k camera and commercially available strain analysis software using a sub 5nm parallel probe. It was observed that doubling the step size of the data acquisition from 5nm per step to 2.5nm per step with a 4k image resolution changed the sensitivity of the data by about 4%. However, increasing the number of pixels of each diffraction pattern from 2k to 4k and removing the focused ion beam prepared sample surface damage both showed greater than 10% improvements in nano beam electron diffraction (NBD) sensitivity greater than 10%. As a result, it is possible to obtain greater sensitivity of the NBD technique by employing these changes in response to the evolving characterization needs.

Cu wires were bonded to AlSi (1%) pads, subsequently encapsulated and subjected to uHAST (un-biased Highly Accelerated Stress Test, 130 °C and 85% relative humidity). After the test, a pair of bonding interfaces associated with a failing contact resistance and a passing contact resistance were analyzed and compared, with transmission electron microscopy (TEM), electron diffraction, and energy-dispersive spectroscopy (EDS). The data suggested the corrosion rates were higher for the more Cu-rich Cu-Al intermetallics (IMC) in the failing sample. The corrosion was investigated with factors including electromotive force (EMF), self-passivation of Al, thickness and homogeneity of the Al-oxide on the IMC, ratio of the Cu-to-Al surface areas exposed to the electrolyte for an IMC taken into account. The preferential corrosion observed for the Cu-rich IMC is attributed to the high ratios of the surface areas of the cathode and anode that were exposed to the electrolyte, and the passivation oxide of Al with the lower homogeneity. The corrosion of the Cu-Al IMC is just a manifestation of the well-known phenomenon of dealloying. With the understanding of the corrosion mechanisms, prohibiting the formation of Cu-rich IMCs is expected be an approach to improve the corrosion resistance of the wire bonding.

In this work, we present TEM failure analysis of two typical failure cases related to metal voiding in Cu BEOL processes. To understand the root cause behind the Cu void formation, we performed detailed TEM failure analysis for the phase and microstructure characterization by various TEM techniques such as EDX, EELS mapping and electron diffraction analysis. In the failure case study I, the Cu void formation was found to be due to the oxidation of the Cu seed layer which led to the incomplete Cu plating and thus voiding at the via bottom. While in failure case study II, the voiding at Cu metal surface was related to Cu CMP process drift and surface oxidation of Cu metal at alkaline condition during the final CMP process.

Aluminum-copper alloys are popular for many applications that take advantage of the combination of properties in the alloys. This paper describes the use of multiple advanced failure analysis tools to analyze the physical and chemical properties of Al-Cu alloy thin films.

The continually shrinking dimensions of today’s semiconductor technology occasionally allow for novel approaches in imaging defects. It has become desirable to image subsurface voids prior to cross sectioning and some efforts have been made to address this need including the construction of specialized instrumentation [1]. The thickness of the metallization levels at the 65 nm technology node and smaller now allow for the use of the electron beam in a scanning electron microscope (SEM) as a material sensor. At high accelerating voltages (between 20-30 kV) in backscatter imaging mode the numerical gray level values at each pixel location can correlate to the amount of material directly under the electron beam at that location. This is particularly evident when dealing with defined geometries and material sets offering high contrast changes between materials such as those found in semiconductor technology like copper (Cu) metal and conventional dielectric materials. As a result, subsurface voids can be mapped to a reasonable representation prior to cross sectioning and precise pinpointing of the defect location in test structures can occur. This paper discusses this methodology on 65 nm technology with Cu metal lines in a low-k dielectric material for a two level metal test structure. To some extent this work represents a natural extension of a paper presented previously by the author [2].

Strained silicon induced by the CMOS device process has been considered an important technology for improving the performance of MOSFETs by increasing local carrier mobility in the current channel. In order to evaluate the feasibility of using convergent beam electron diffraction (CBED) in lattice strain determination, high-order Laue zone (HOLZ) lines inside the center disc of a CBED pattern with specific zone axes were kinematically simulated. The intersecting HOLZ lines shift was plotted against the lattice parameter for the determination of uniaxial strain.

Both the increased complexity of integrated circuits, resulting in six or more levels of integration, and the increasing use of flip-chip packaging have driven the development of integrated circuit (IC) failure analysis tools that can be applied to the backside of the chip. Among these new approaches are focused ion beam (FIB) tools and processes for performing chip edits/repairs from the die backside. This paper describes the use of backside FIB for a failure analysis application rather than for chip repair. Specifically, we used FIB technology to prepare an IC for inspection of voided metal interconnects (“lines”) and vias. Conventional FIB milling was combined with a superenhanced gas assisted milling process that uses XeF2 for rapid removal of large volumes of bulk silicon. This combined approach allowed removal of the TiW underlayer from a large number of M1 lines simultaneously, enabling rapid localization and plan view imaging of voids in lines and vias with backscattered electron (BSE) imaging in a scanning electron microscope (SEM). Sequential cross sections of individual voided vias enabled us to develop a 3D reconstruction of these voids. This information clarified how the voids were formed, helping us identify the IC process steps that needed to be changed.

A wealth of literature has arisen in the past couple of decades regarding the phenomenon of electromigration. In addition, stress voiding has received considerable attention from the research community. Some of the work on the structural character of these phenomena has focussed on the roles of crystallographic texture and grain boundary structure. It is an experimental fact that the strength of the (111) fiber texture is an indication of interconnect reliability, the stronger the texture, the more reliable the interconnect. It is also presumed that grain boundary diffusivity is a controlling factor in electromigration behavior of polycrystalline lines. Undesirable grain boundary structure is likely a cause of failure in lines with a bamboo structure as well because they are often sites of stress concentration and local incompatibilities. The present study focuses upon electromigration failures in test structures of Al-Cu lines and stress voiding in Cu lines. Texture and grain boundary structure were measured directly on the specimens using electron back-scatter diffraction and orientation imaging. It is observed that a correlation exists between grain boundary structure and void formation in strongly textured polycrystalline lines. Results indicate that secondary orientation (not just the (111) fiber), and boundary structure may be of primary importance in optimizing interconnect microstructure.