Power devices technology and in particular devices based on 4H-SiC require a thick metal layer in top to make a source contact and on the backside to make a drain contact. These metal layers are the main problem for fault isolation activities. Up today, many fault isolation techniques do not allow for results, and it is mandatory to remove this layer before performing them. During the metal removal on wafer there is a high probability of damaging the sample or breaking the wafer, especially if the latter is very thin. In this analysis we show a methodology that allows fault isolation analysis, performed on wafers with metal layers, preventing the risks of sample damage induced from preparation.

In the field of failure analysis of integrated circuits, diagnosing functional failures is a requirement. Traditional beam-based analysis techniques use a scanning laser or ebeam to induce a parametric shift, which is monitored through changes in current or voltage driven to the device. Deep submicron technologies frustrate these analytical methods due to the nearly immeasurable parametric shifts externally caused by a small signal leakage path internally. These internal failures can be identified functionally by timing, temperature or voltage dependencies but the exact location of the fault is difficult to isolate. SIFT (Stimulus Induced Fault Test), RIL (Resistive Interconnect Localization) and SDL (Soft Defect Localization) can identify anomalies functionally using induced thermal gradients to the metal but does not address how to analyze embedded temperature sensitive defects inaccessible to the laser. 1,2,3,4 Stacked die and similar 3 dimensional (3D) devices complicate the analysis requiring destruction/removal of one or more die. This paper will show how to create quantifiable thermal gradients to a defect and triangulate the location of the defect in 1, 2, and 3 dimensions as follows: 1. Apply a differential temperature gradient across the device in each of the X,Y, and Z-axes. The defect is localized based on its measured response in the gradient as the gradient sweeps across. 2. Induce a gradient with a laser and use the measurement of DC power required to relate the distance to the defect from various locations in relation to a heat sink. 3. Measure the time of flight of the thermal propagation to a defect from known laser positions to triangulate the location of the defect.

The presence of gold within a Sn/Pb solder joint accelerates diffusion between the Sn and Ni of the Ni- V/Cu underlying bump metallurgy (UBM), generating early failures. A concentration of 1.2 wt% gold in the solder joint can accelerate time to failure by a factor of 400 [3]. The EDS x-ray microanalysis detection limit for gold in tin / lead solder of about 1.2 wt% gold was found to be above the concentration range of interest (0.1 – 0.5 wt% gold). Due to the reliability impact that even a low concentration of gold can have on solder joints employing Ni-V/Cu UBM, a method using differential scanning calorimetry (DSC) was developed to accurately measure gold concentrations of less than 1 wt% in solder bumps.