In the field of failure analysis (FA) for semiconductor devices, the transmission electron microscope (TEM) as an analytical tool is integral to finding visible evidence of defects and their root cause. Especially as device features shrink, imaging and analyzing increasingly subtle defects requires detailed elemental analysis. In this work, elemental analysis using an aberration-corrected TEM at different accelerating voltages (200 kV and 80 kV) is discussed. The impact of accelerating voltage on elemental analysis with regards to Electron Energy Loss Spectroscopy (EELS) and Energy Dispersive X-Ray Spectroscopy (EDS) is of central focus. Two case studies involving TEM samples of different thicknesses are presented that clearly indicate important differences in the analytical data collected at different accelerating voltages. The work revealed that for elemental analysis of thick TEM samples (100 nm and over) 200 kV is preferred, and for thin samples, 80 kV provides superior signal in EDS and EELS.

Power MOSFETs are electronic devices that are commonly used as switches or amplifiers in power electronics applications such as motor control, audio amplifiers, power supplies and illumination systems. During the fabrication process, impurities such as copper can become incorporated into the device structure, giving rise to defects in crystal lattice and creating localized areas of high resistance or conductivity. In this work we present a multiscale and multimodal correlative microscopy workflow for the characterization of copper inclusions found in the epitaxial layer in power MOSFETs combining Light Microscopy (LM), non-destructive 3D X-ray Microscopy (XRM), Focused-Ion Beam Scanning Electron Microscopy (FIB-SEM) tomography coupled with Energy Dispersive X-ray Spectroscopy (EDX), and Transmission Electron Microscopy (TEM) coupled with Electron Energy Loss Spectroscopy (EELS). Thanks to this approach of correlating 2D and 3D morphological insights with chemical information, a comprehensive and multiscale understanding of copper segregations distribution and effects at the structural level of the power MOSFETs can be achieved.

Static random-access memory (SRAM) is a type of device that requires the highest reliability demands for integration density and process variations. In this study, we focus on single bit cell SRAM failures. These failures can be categorized as Hard bit cell failure, where bit cells fail the read or write operation under both higher and lower supply voltages, and Soft Bit cell failure, where failures occur at either higher or lower voltage. The analysis on SRAM Soft failure is further divided as VBOX High and VBOX Low failure, which depends on the failure mode supply voltage. With transistor dimensions continuously shrinking, the analysis of SRAM errors imposes tremendous challenges due to their small footprint. In this paper, a thorough failure analysis procedure is described for solving an SRAM yield loss issue. Different analysis techniques were applied and compared to narrow down the failure to the final root cause, including nanoprobing, Focus Ion Beam (FIB) cross-section, Scanning Spreading Resistance Microscopy (SSRM), Transmission Electron Microscopy (TEM), Electron Energy Loss Spectroscopy (EELS), Scanning Capacitance Microscopy (SCM), and stain etch.

This presentation shows how transmission electron microscopy (TEM) is used in semiconductor failure analysis to locate and identify defects based on their physical and elemental characteristics. It covers sample preparation methods for planar, cross-sectional, and elemental analysis, reviews the capabilities of different illumination and imaging modes, and shows how beam-specimen interactions are employed in energy dispersive (EDS) and electron energy loss spectroscopy (EELS). It describes the various ways transmission electron microscopes can be configured for elemental analysis and mapping and reviews the advantages of scanning TEM (STEM) approaches. It also provides an introduction to energy-filtered TEM (EFTEM) and how it compares with other TEM imaging techniques.

This paper describes the investigation of donut-shaped probe marker discolorations found on Al bondpads. Based on SEM/EDS, TEM/EELS, and Auger analysis, the corrosion product is a combination of aluminum, fluorine, and oxygen, implying that the discolorations are due to the presence of fluorine. Highly accelerated stress tests simulating one year of storage in air resulted in no new or worsening discolorations in the affected chips. In order to identify the exact cause of the fluorine-induced corrosion, the authors developed an automated inspection system that scans an entire wafer, recording and quantifying image contrast and brightness variations associated with discolorations. Dark field TEM images reveal thickness variations of up to 5 nm in the corrosion film, and EELS line scan data show the corresponding compositional distributions. The findings indicate that fluorine-containing gases used in upstream processes leave residues behind that are driven in to the Al bondpads by probe-tip forces and activated by the electric field generated during CP testing. The knowledge acquired has proven helpful in managing the problem.

The State-of-the-Art FinFET technology has been widely adopted in the industry, typically at 14 nm and below technology nodes. As fin dimensions are pushed into the nanometer scale, process complexity is highly escalated, posing great challenges for physical failure analysis. Meanwhile, the accelerated cycles of learning for new technology nodes demand high accuracy and fast turnaround time to solve the material and interface issues pertaining to semiconductor processing or device failure. In this paper, we report a case study of fin related defect that caused device failure. Several analytical techniques, namely, Scanning Electron Microscopy (SEM), plan-view and cross-section Transmission Electron Microscopy (TEM) with Energy Dispersive X-ray spectroscopy (EDX), Electron Energy Loss Spectroscopy (EELS) and Z-contrast tomography were employed to characterize the defect and identify root-cause, leading to the resolution of this issue.

The plasmon-loss region of the low-loss electron energy loss spectroscopy (EELS) contains chemical information similar to core-loss EELS; therefore it can be utilized as finger-printing elements. A high throughput phase mapping technique based on plasmon energy (Ep) is proposed. We have successfully applied this phase mapping technique into two case studies in our magnetic head manufacturer processes. This Ep phase mapping can be applied to not only the data storage but also semiconductor industries.

Forming and breaking a nanometer-sized conductive area are commonly accepted as the physical phenomenon involved in the switching mechanism of oxide resistive random access memories (OxRRAM). This study investigates a state-of-the-art OxRRAM device by in-situ transmission electron microscopy (TEM). Combining high spatial resolution obtained with a very small probe scanned over the area of interest of the sample and chemical analyses with electron energy loss spectroscopy, the local chemical state of the device can be compared before and after applying an electrical bias. This in-situ approach allows simultaneous TEM observation and memory cell operation. After the in-situ forming, a filamentary migration of titanium within the dielectric hafnium dioxide layer has been evidenced. This migration may be at the origin of the conductive path responsible for the low and high resistive states of the memory.

In this article, an analysis of a failure in the embedded SRAM in a CMOS Image Sensor is investigated. The failure was due to unformed CoSi2. Because unformed CoSi2 causes a varying degree of response, a nano-prober was used to find the abnormally operating transistors among a 1-bit SRAM cell consisting of six transistors(6T). After measuring and analyzing the current-voltage relationships between each transistor, the current magnitude of one pull-down transistor was found to be less than the expected range and particularly lower than that of a connected access transistor. To visualize the failure phenomenon and find the root cause of this, TEM analysis was conducted. Using the EELS (Electron Energy Loss Spectroscopy) elemental mapping, unformed CoSi2 was detected between the contact and substrate, where the contact corresponds to the VSS of the pull-down transistor. This caused an increase in the contact resistance, thus lowering the current magnitude of the abnormal transistor to a greater degree than expected.

In this work, we present TEM failure analysis of two typical failure cases related to metal voiding in Cu BEOL processes. To understand the root cause behind the Cu void formation, we performed detailed TEM failure analysis for the phase and microstructure characterization by various TEM techniques such as EDX, EELS mapping and electron diffraction analysis. In the failure case study I, the Cu void formation was found to be due to the oxidation of the Cu seed layer which led to the incomplete Cu plating and thus voiding at the via bottom. While in failure case study II, the voiding at Cu metal surface was related to Cu CMP process drift and surface oxidation of Cu metal at alkaline condition during the final CMP process.

The failure analysis using transmission electron microscopy (TEM) has been actively preceded in semiconductor industry. But due to the overlap issue and structural complexity of devices, it has become harder and harder to perform failure analysis using normal projected bright field (BF) and high angle annular dark field (HAADF) TEM images. To overcome these problems, 3-dimensional (3D) tomography technique has been suggested. In this work, we clarify the root cause of dark voltage contrast (DVC) failure at the bottom electrode contact region in PCRAM by using 3D tomography analysis. The 3D tomography samples were prepared in lamella shape by using focused ion beam (FIB). The electron energy loss spectroscopy (EELS) and 3D tomography analysis in scanning transmission electron microscope (STEM) HAADF mode were carried out. Through 3D tomography image reconstruction by AMIRA program, we observed ‘open contact fail’ between the BEC (Bottom Electrode Contact)-1 and the BEC (Bottom Electrode Contact)-2 at DVC region that could not be shown in 2D image.

Inclusion of cerium (Ce) oxide particles as an abrasive into chemical mechanical planarization (CMP) slurries has become popular for wafer fabs below the 45nm technology node due to better polishing quality and improved CMP selectivity. Transmission electron microscopy (TEM) has difficulties finding and identifying Ce-oxide residuals due to the limited region of analysis unless dedicated efforts to search for them are employed. This article presents a case study that proved the concept in which physical evidence of Ce-rich particles was directly identified by analytical TEM during a CMP tool qualification in the early stage of 20nm node technology development. This justifies the need to setup in-fab monitoring for trace amounts of CMP residuals in Si-based wafer foundries. The fact that Cr resided right above the Ce-O particle cluster, further proved that the Ce-O particles were from the wafer and not introduced during the sample preparation.

Transmission electron microscope based elemental analysis techniques utilize X-ray photons in EDS and inelastically scattered electrons or the energy-loss electrons in electron energy-loss spectroscopy and energy-filtered transmission electron microscopy (EFTEM). This paper discusses the applications of EFTEM to visualize polysilicon defects, gate dielectric and silicon nanocrystals using inelastically scattered low energy-loss electrons. It focuses on features that are primarily composed of silicon and silicon-oxide. Various benefits of using plasmon energy-loss electrons to image silicon nanocrystals layer in thin film storage device are also outlined. Even though this work has focused on low-loss imaging of features and defects in the front-end of the process based on silicon/silicon-oxide integrated circuits, these techniques can also be applied to technologies based on other materials by selecting appropriate plasmon peaks corresponding to those materials.

Electrical resistance of M1/M3 stack for Aluminium based technology showed anomalous values when no Ti is inserted between AlCu and cap TiN. Process investigations lead to suspect formation of AlN layer at this interface. Blanket wafers were processed at different temperatures to reproduce the layer formation and characterize the film by numerous techniques including XPS and EELS-TEM profiling. Full use of the different results shows the formation of a very thin (a few nms) and highly resistive AlN layer at the cap TiN / AlCu interface as well as a thicker but less resistive AlN layer at the bottom TiN / AlCu interface. PVD process changes were attempted to reduce the M1/M3 button stack resistance. Modification of the N2/Ar flow ratio for TiN sputtering shows slightly more stoechiometric TiN with reduced stack resistance by 35%.

A framework is presented for considering the relative strengths of Auger electron spectroscopy (AES)/scanning Auger microscopy (SAM) and scanning transmission electron microscopy–electron energy loss spectroscopy (STEM-EELS) when selecting a defect analysis technique. The geometry of the analysis volumes for each technique is visualized. The analysis volume for AES/SAM is shaped like a button while the STEM-EELS analysis volume is more like a thread extending throughout the thickness of the prepared sample. The usefulness of this framework is illustrated with the example of small defect particles. In this example the size and shape of the AES/SAM analysis volume is a better fit to the defect, thus it provides better chemical analysis while STEM provides better images of the defects.

A 300 keV TEM equipped with an EELS and energy selected imaging (ESI) system has proven to be a necessary and powerful analytical tool for R&D and failure analysis support. The advantages and the efficacy of this advanced elemental mapping technique can be optimized when the TEM is operated correctly. Variants of ESI, elemental mapping, jump-ratio mapping, and pre-edge imaging have been adapted to explore root causes of different type of failures in semiconductor manufacturing.

This paper discusses the challenges involved in testing microprocessors incorporating silicon-on-insulator (SOI) technology and assesses new characterizations tools, such as scanning capacitance microscopy (SCM), focused ion beam (FIB) analysis, and AFM electrical probing, that show promise when used to examine SOI device anomalies and failure modes.