This presentation shows how transmission electron microscopy (TEM) is used in semiconductor failure analysis to locate and identify defects based on their physical and elemental characteristics. It covers sample preparation methods for planar, cross-sectional, and elemental analysis, reviews the capabilities of different illumination and imaging modes, and shows how beam-specimen interactions are employed in energy dispersive (EDS) and electron energy loss spectroscopy (EELS). It describes the various ways transmission electron microscopes can be configured for elemental analysis and mapping and reviews the advantages of scanning TEM (STEM) approaches. It also provides an introduction to energy-filtered TEM (EFTEM) and how it compares with other TEM imaging techniques.

This presentation provides an introduction to atomic force microscopy (AFM) and its many uses in semiconductor failure analysis. It provides examples showing how AFM is used to obtain information on electric fields, surface potential, current, resistance, capacitance, impedance, carrier concentration, mechanical contact (height and energy dissipation), temperature, and composition. It also addresses a number of related issues including the use of external stimuli, sample preparation requirements, and probe tip selection.

This presentation covers the challenges associated with IC package inspection and shows how two nondestructive techniques, scanning acoustic microscopy and X-ray imaging, are being used to locate and identify a wide range of defects, particularly those in 3D packages and multilayer boards. It reviews the basic principles of scanning acoustic microscopy (SAM), X-ray imaging, and 3D X-ray tomography and the factors that affect image resolution and depth. It demonstrates the current capabilities of each method along with different approaches for improving resolution, contrast, and measurement time.

There are several variants of artificial intelligence (AI) hardware structures that are under study by the semiconductor industry for potential use in complementary metal–oxide–semiconductor (CMOS) designs. This paper discusses some of the failure analysis challenges that have appeared in discrete test structures and test arrays developed as part of an exploratory phase-change memory (PCM) program at IBM's Albany AI Hardware Research Center.

This paper describes a project to develop and deploy a systematic screening methodology involving computed tomography (CT) to inspect a set of electromagnetic interference (EMI) filter components for a spacecraft application. The goal was to deploy the nondestructive CT test to replace the destructive test method typically deployed for such components. The paper describes the development of test criteria, fixturing, inspection process, and data analysis, including quantitative image analysis of voids and cracks. The initial results indicated that the parts would not pass the requirements established in the test design. A waiver was written to the project clarifying that if the parts were to be used in the assembly, they should be considered as simple conductors with EMI filtering capability viewed as an added benefit rather than a guaranteed design requirement.

In this paper, we demonstrate with a case study on a nanocapacitor, the capability of transmission electron microscopy in electron holography mode to be a unique in-situ technique for mapping electric fields and charge distributions on a single device. Such precision is necessary to keep pace with shrinking device dimensions and the ever increasing complexity of device architectures.

This paper discusses the use of optical photothermal infrared (O-PTIR) spectroscopy combined with Raman analysis. The new technique overcomes many of the limitations of conventional FTIR and Raman spectroscopy when used alone. It is based on an infrared-visible pump-probe system that incorporates a wavelength-tunable IR laser that emits a pulsed beam that is combined colinearly with the output of a 532-nm green laser. As the paper explains, infrared radiation is partially absorbed by the test target when the wavelength of the laser resonates with the vibrational mode of the material. This excitation process causes the area under the infrared spot to heat up, in turn, causing local expansion along with changes in the refractive indices. These photothermal effects cycle on and off in synch with the pulsed IR beam and the amplitudes of the on-off states are captured by the co-located visible beam and plotted as a function of wavelength over the tunable range of the IR laser. The diffraction limited spot size of the visible beam is approximately 416 nm, corresponding to a spatial resolution of about 1 μm, which is 30 times more precise than conventional FTIR. In addition, by measuring photothermal effects in localized regions, it is possible to identify chemicals in quantities of matter as small as 0.4 pg. By comparison, the sensitivity of transmission mode FTIR is significantly less at around 100 pg.

In this paper, we describe the technique of on-axis transmission Kikuchi diffraction (TKD) in a scanning electron microscope and demonstrate its use in characterizing nanoscale crystal structures and defects in semiconductor materials and devices. We explain how we modified hardware and software to achieve an effective spatial resolution of 2 nm during orientation mapping without decreasing acquisition speed, indexing quality, and other performance parameters. The paper includes illustrations comparing sample-detector geometries for conventional EBSD, TKD, and on-axis TKD. It also presents examples of the types of images that can be obtained using on-axis TKD, including raw crystal orientation maps, diffraction patterns, pattern quality maps, time-resolved orientation maps showing microstructure evolution, and a sparse sample map showing the distribution of quantum dots on an electron transparent support film.

This paper explains how nanoprobe analysis was used to determine the cause of data retention failures in nonvolatile memory (NVM) bitcells. The challenge with such memory cells is that they consist of two transistors with a single control gate in series with a programmable floating gate connected by a shared source/drain active area. With such a layout, there is no way to isolate the control gate from the floating gate, meaning that characterization must be performed simultaneously on both transistors. Having to characterize two transistors connected in series increases the number of potential electrical signature effects not by a factor of two, but rather the power of two, which makes interpreting the results much more difficult. As discussed in the paper, however, the authors used an atomic force probe to verify the bit map of the faulty device and then analyze the failing bit to confirm the programming error and reveal the possible failure mechanism. The failure mechanism was determined based on its electrical signature and a physical analysis of the bitcell location.

This paper presents a number of case studies in which various methods and tools are used to localize resistive open defects, including two-terminal IV, two-terminal electron-beam absorbed current (EBAC), electron beam induced resistance change (EBIRCH), pulsed IV, capacitance-voltage (CV) measurements, and scanning capacitance microscopy (SCM). It also reviews the advantages and limitations of each technique.

In this paper, we describe the difference between oscilloscope pulsing tests and waveform generator fast measurement unit (WGFMU) tests in analyzing high-resistance defects in DRAM main cells. Nanoprobe systems have various constraints in terms of pulsing whether it involves an oscilloscope or pulse generator. There are certain types of devices, such as DRAM cells, for which these systems are ineffective because saturation currents are too small. In this paper, we address this constraint and propose a new way to conduct pulsing tests using the WGFMU's arbitrary linear waveform generator in combination with an electro-optical nanoprobe.

This paper presents a novel approach for detecting channel hole bending (ChB) defects in vertical NAND flash memory. Such defects are the result of etching process inconsistencies and contribute to data loss and device failure by inducing leakage current between adjacent channel holes. In order to satisfy long-term reliability requirements and volume demand, chipmakers must be able to detect these defects prior to shipping during electrical die sorting and screening procedures. The proposed method works by monitoring leakage current differences between diagonally and horizontally adjacent memory cells and is shown to be an effective screening technique.

This paper describes the development and implementation of a TEM-based measurement procedure and shows how it is used to determine the verticality or etching angle of channel holes in V-NAND flash with more than 200 layers of memory cells. Despite the high aspect ratio of the region of interest, the method can resolve offsets down to a few nm. Such precision is critical, as the paper explains, because the radius and thus electrical characteristics of each memory cell is determined by the etching angle.

This paper presents a fast and accurate method for identifying defects responsible for SRAM bitcell failures. The steps involved in the process include functional testing, current-voltage measurements, and defect classification based on electrical failure analysis data. The entire procedure takes less than two hours and works for both hard and soft defects as well as reliability failures. A case study is included in the paper to demonstrate the efficiency of the nondestructive technique.

This paper explains how embedded assist and timing control techniques are being used to improve soft defect screening in nanoscale static random access memory (SRAM). The electrical stress test method is evaluated on advanced FinFET devices. As test results show, resistive and parametric defects that are difficult if not impossible to detect using conventional techniques become visible with the aid of assist and timing control circuits.

Defects associated with metal-insulator-metal (MIM) capacitor failures can be difficult to locate using conventional fault isolation techniques because the capacitors are usually buried within a stack of back-end metal layers. In this paper, the authors explain, step by step, how they determined the cause of MIM capacitor failures, in one case, in an overvoltage protection device, and in another, a high-speed digital isolator circuit. The process begins with a preliminary fault isolation study based on OBIRCH or PEM imaging followed by more detailed analyses involving focused ion beam (FIB) cross-sectioning and delayering, micro- or nano-probing, resistive or voltage contrast imaging, and other such techniques.

This paper discusses the development of an electrical failure analysis workflow that uses a multifunction direct current tester (DCT) to map the location of defects associated with open and short circuits as well as leakage current. It explains how software and tooling were designed to accommodate a wide range of package types and sizes and how they were verified by testing. It also presents two case studies showing the accuracy of the defect mapping function for sockets with 0.8 and 1.0 mm ball pitch.

This paper presents an alternative approach for analyzing complex scan chain failures in which there are multiple candidates that could be the root cause. It demonstrates the approach on an automotive IC with several failing flip-flops. An analysis of the interconnections shared by the failing devices reveals a common clock branch where the root cause is likely to reside. Photo-emission microscopy (PEM) is then used to verify the existence of a defect which, based on passive voltage contrast, is determined to be an open path.

This paper presents a user-defined fault model (UDFM) that accounts for silicon behaviors that cannot be explained using traditional stuck-at and transition delay fault models. The new model targets cell-internal faults but does not require time-intensive SPICE simulations because it operates at the logic level. As added benefit, error logs collected using UDFM patterns (instead of traditional models) can be used to generate diagnostic callouts with improved resolution. A workflow that effectively achieves this is presented in the paper along with three case studies that demonstrate the usefulness of the proposed method.

For unique single failures, which tend to be the case in customer return and reliability failures, selecting another sample or performing root cause deconvolution is not an option, and if diagnostic tests are not conclusive, it becomes necessary to extend the effectiveness of automatic test pattern generator (ATPG) diagnosis in order to determine the failure mechanism. This paper proposes a way to improve resolution using single-shot logic and high-resolution targeted patterns. Two cases are presented to demonstrate the approach and show how it performed on actual failing units.