Soft defect localization (SDL) is a fault isolation (FI) technique used to root cause device marginalities and/or defects. The variety of test modes and their marginalities that can be solved with SDL is increasing as we find new ways to utilize this technique to our needs. However, SDL analysis can be time consuming if the test times are slow since millions of test executions are needed to get a statistically significant result. To solve this problem, we propose an improvement named software automated intelligent laser scanning (SAILS) to modulate laser dwell time on the fly. This software and hardware implementation can be applied to any test method, now or in the future, and to any of the SDL tools available in the market. In this paper, we discuss the successful implementation of this approach and show its ability to judiciously mask out sites in real-time and use this mask to modulate laser dwell time.

The occurrence of electrical overstress (EOS) failure in low-voltage core circuits resulting from latch-up test at the I/O pins was investigated, where a specific commercial IC product equipped with on-chip low-dropout regulator (LDO). Through failure analysis experiments, the root cause of EOS failures is identified to the abnormal LDO output voltage during latch-up test. In this work, a modified design featuring a deep n-well (DNW) beneath the NMOS region is proposed to mitigate EOS issue by enhancing electron absorption. Additionally, compensation network configurations are explored to explain the abnormal LDO operation. The experimental results from test chip have validated the effectiveness of the proposed modifications, emphasizing the importance of proactive measures in mitigating EOS failures.

Air-assisted liquid cooling (AALC) has emerged as a preferred cooling solution for data centers housing traditional air-cooled server racks, owing to its straightforward integration with existing infrastructure. However, the rising power demands of AI hardware (30-100kW per rack) and its variable computational loads generate unprecedented heat levels that challenge system reliability and uptime. Through long-term reliability testing of AALC systems, we identify and analyze unique failure mechanisms associated with liquid cooling implementations. This paper presents our findings on system vulnerabilities, details the failure analysis methodology, establishes root causes, and outlines the corrective measures implemented to enhance AALC system reliability in high-performance computing environments.

Unique frequency dependent hold time violation debug seen on Ethernet IP that caused at least 50% yield loss is showcased in this paper. This debug exposed the process variation issue seen, limitation in current FPGA timing sign-off methodology and design limitation that led to this rare hold time behavior. Customized ATPG patterns has become de facto for effective HVM screening including exploration of new path hold time fault pattern generation. The debug was backed by tester level and system validation debug with help from optical probing and FIB to confirm the root cause and silicon fixes required.

Integrated circuit (IC) de-processing is a crucial step in failure analysis (FA) for defect validation and root cause identification. The commonly used FA de-processing technique is top-down delayering, this is because of faster and easier for sample preparation. However, backside de-processing is occasionally necessary for fault isolation, better root cause understanding, and formulating the failing mechanism such as gate oxide defects, front-end of line (FEOL) defects, back-end of line (BEOL) vertical shorts, high power Ga-N on Silicon (Si) substrate device, etc. This paper introduces an innovative backside de-processing method for ICs utilizing laser ablation by employing a commercial laser decapsulation system. We thin the backside Si substrate via laser ablation and subsequent chemical etching, revealing FEOL defects. Experimental results demonstrate the method's efficiency, offering enhanced sample handling and reduced preparation time. The proposed backside laser de-processing technique proves to be a superior choice compared to conventional methods in terms of success rate, de-processing speed, and cost-effectiveness. This research contributes to advancing FA methodologies by introducing an innovative approach for backside physical FA applications, opening new possibilities for efficient and accurate IC analysis.

In advanced chip package failure investigations, Electro Optical Terahertz Pulse Reflectometry (EOTPR) simulation emerges as a highly effective fault isolation technique. However, traditional manual methods for generating simulation models face significant challenges, including laboriousness, time consumption, and susceptibility to human error. To address these obstacles, we have developed an automation software script in-house. This script autonomously interfaces with the design database, extracting crucial trace information and generating an optimized equivalent trace model. This automated process markedly enhances the efficiency of EOTPR model simulations, streamlining workflow, standardizing procedures, and reducing the potential for human error. The efficacy of integrating the automation script into the workflow of advanced package failure analysis was demonstrated through two case studies. This integration significantly enhanced productivity and enabled successful root-cause investigation of advanced package failures.

The semiconductor industry is no longer driven purely by performance. Miniaturization, increased functionality, low latency and high bandwidth requirements are becoming more important. Furthermore, as Moore’s law scaling becomes more difficult and costly, innovations in packaging technologies through heterogeneous integration are being adopted rapidly to meet these demands. This paper discusses how defects in InFO (Integrated Fan-Out) wafer level multi-die semiconductor packages can be successfully root caused and describes the challenges faced when doing failure analysis of such packages.

The rise of 2.5D and 3D heterogeneous integrated devices presents unique challenges for failure analysis, as traditional 2D analysis techniques prove inadequate due to chip stacking, layer interconnects, die obscuration, and limited access to test points. While various non-destructive techniques—including 3D X-ray imaging, lock-in thermography, magnetic field imaging, and optical beam methods—offer partial solutions, each has specific limitations. We present a novel defect localization approach using radio frequency electromagnetic (EM) emanations, implemented in two ways: detecting EM signals emitted by the device under controlled input conditions, or measuring induced voltage responses to signals injected via a scanning antenna. The technique employs scanning magnetic or electric field antennas to generate 2D or 3D electromagnetic maps revealing current and electric continuity patterns, enabling detection of shorts (additional current paths) or opens (blocked current paths). By incorporating power spectrum analysis (PSA) at each scan point, our method—designated as EM antenna PSA (EMAPSA) or EM injection PSA (EMIPSA)—provides comprehensive defect detection capabilities for 3D heterogeneous integration failure analysis.

The job of yield and failure analysis (YA and FA) engineers is to identify the root cause of low-yielding wafers. While physical FA is the most definitive method for determining root cause, resource limitations require YA engineers to search for root cause by identifying other wafers with similar yield signatures. The immense number of yield parameters, or features, collected in modern semiconductor processes makes this a difficult task. This paper presents a workflow employing multiple AI techniques to separate groups of wafers by their distinct yield signatures and determine the parameters most important to defining each group. This aids in the disposition of new low-yield wafers, maximizes the learning from previously collected FA wafers, and allows FA resources to be allocated more effectively, prioritizing them for the highest-impact, unknown fail modes.

This paper presents a root cause analysis case study of defective Hall-effect sensor devices. The study identified a complex failure mode caused by chip-package interaction, which has a similar signature to discharging defects such as ESDFOS. However, the study revealed that the defect was induced by local mechanical force applied to IC structures due to the presence of large irregular-shaped filler particles within the mold compound. Extensive failure analysis work was conducted to identify the failure mode, including the development of a new backside analysis strategy to preserve the mold compound during IC defect localization and screening. A combination of different failure analysis techniques was used, including CMP delayering, PFIB trenching, SEM PVC imaging, and large area FIB cross-sectioning. The study found that the mold compound of the package caused thermos-mechanical strain onto the silica filler particle due to epoxy shrinkage during the molding process. Additionally, extra-large, irregularly shaped filler particles (called twin particles), located on top of the chip surface, can cause locally high compression stresses onto the IC layers, initiating cracks in the isolation layers under certain conditions forming a leakage path over the time. Thermo-mechanical finite element analysis was applied to verify the mechanical load condition for these large irregular-shaped filler particles. As a result, an additional polyimide layer was introduced onto the IC to mitigate the mechanical stress of mold compound particles to avoid this failure mode.

Photon Emission Microscopy (PEM) is a popular technique for microelectronics failure analysis by detecting the photon emission from a defective circuit, when a failing device is electrically exercised at certain voltage. The photon emission contains physical location information, photon emission spectral information and photon emission intensity information. People often use the physical location information to localize a defective circuit and guide the follow-up physical failure analysis to find the defects. However, this procedure does not always work. Sometimes, it shows no defect found (NDF). In this paper, we propose a new computer vision-based analysis of the photon emission intensity for identifying the root cause of the excessively high IDDQ at elevated Vdds. The procedure includes collecting photon emissions at different Vdds and a follow-up photon emission intensity analysis with computer vision techniques. The procedure was applied on a case of microprocessor chip. After analyzing the dependencies of photon emission intensity on Vdd for 4 types of circuits, it was concluded that the SRAM circuit leakage is the root cause of the excessively high IDDQ at elevated Vdd.

We present the first experimental demonstration of on demand bit-level Static Random Access Memory (SRAM) validation and isolation through the exploitation of a continuous wave (CW) 785nm Laser-Induced Fault Analysis (LIFA) system. Through careful test pattern edits and the observation of a simple pass/fail flag, the ability to spatially map the physical location of pre-selected bits in 40nm, 16nm, and 5nm SRAM arrays using correlation units is confirmed. This work demonstrates a novel and highly-efficient methodology for rapid bit-level logical-to-physical identification. It also improves localization efficacy over conventional bitmap validation best-known methods (BKM) which typically rely on post-fail Photo-Emission Microscopy (PEM) and/or Soft Defect Localization / Laser-Assisted Device Alteration (LADA) performed on an actual fail unit. This new technique re-defines the state-of-the-art in SRAM bitmap validation and localization and offers a pathway to significantly improve cycle time for both product bitmap qualification and subsequent root cause identification.

Continued advancements in the architecture of 3D packaging have increased the challenges in fault isolation and failure analysis (FA), often requiring complex correlative workflows and multiple inference-based methods before targeted root cause analysis (RCA) can be performed. Furthermore, 3D package components such as through-silicon-vias (TSVs) and micro-bumps require sub-surface structural characterization and metrology to aid in process monitoring and development throughout fabrication and integration. Package road-mapping has also called for increased die stacking with decreased pitch, TSV size, and die thickness, and thus requires increased accuracy and precision of various stateof- the-art analytical techniques in the near future. Physical failure analysis (PFA), process monitoring, and process development will therefore depend on reliable, high-resolution data directly measured at the region of interest (ROI) to meet the complexity and scaling challenges. This paper explores the successful application of plasma-FIB (PFIB)/SEM techniques in 2D and 3D regimes and introduces diagonal serial sectioning at package scales as a novel approach for PFA and metrology. Both 2D and 3D analysis will be demonstrated in a high bandwidth memory (HBM) package case-study which can be applied more broadly in 3D packaging.

Several failures in Chip-On-Lead (COL) package from the customer were returned for Failure Analysis (FA). Containment activities were able to find similar failures. The connectivity of the silicon die to the leads uses gold wire. The die is in live bug position with respect to the package and is being held in place using non-conductive die attach epoxy. The identification of the Failure Mechanism (FMECH) utilized analysis flow involving non-destructive and destructive FA techniques. A hairline crack was found on the die between the two (2) corner pins. Based on lot history reviews, hairline die crack had a very low detectability at electrical test. Further collaboration with the process owners showed the need to identify the crack initiation, propagation and the factors that could result to this FMECH. Analysis of fracture or fractography was utilized in identifying the crack initiation point and propagation. Due to low detectability, identifying the factors resulting to die crack would require several evaluations and process mappings. Finite element analysis (FEA) was utilized to create models and simulation to identify factors that would result to highly stressed area identified through fractography. These additional data for the hairline crack were vital on the identification of root cause and formulation of corrective/preventive actions.

This presentation provides an overview of the terminology and concepts associated with semiconductor yield analysis, modeling, and improvement techniques. It compares and contrasts yield models and describes the steps and equipment involved in setting up yield engineering programs targeting specific failures and defects. It also includes case histories showing how different yield analysis models have been used to identify the root cause of random and systematic failures.

This presentation provides a systematic approach for assessing contamination risks in semiconductor manufacturing environments and determining an appropriate course of action. It maps out a typical wafer production line and identifies potential entry points for specific contaminants. It explains how to perform a contamination risk assessment and prioritize action items and how to select an analytical technique based on where, in the stack, the contaminant resides. It highlights the differences between direct and indirect techniques and shows where they are likely to be used. It also presents a detailed analytical decision flow chart and three concise case studies.

In the failure analysis (FA) of an organic light emitting diode (OLED) display device, fault isolation and physical failure analysis (PFA) were used to identify the root cause of display failure. It is challenging to conduct the FA of a display device, as it consists of display panel, a circuit board and components like semiconductor chips and this integration makes the failure complicated and difficult to analyze and understand. In the case of the display failure studied in this paper, the first work of fault isolation did not clearly identify the origin of the malfunction and its PFA didn’t show any specific defects. To precisely identify the defect location before destructive analysis, the fault isolation technique of OBIRCH was applied to the display device and subsequent PFA successfully identified a crack defect causing the display failure. This finding was given as feedback to the wafer fab and processing parameters were adjusted to prevent generation of the defect in the OLED display device.

The high temperatures and thermal cycling experienced by integrated circuit packages can induce warpage that in turn can lead to cracks developing at material interfaces that compromise the integrity of electrical traces within the device. In this study, the authors demonstrate how Electro-Optical Terahertz Pulsed Reflectometry (EOTPR) with dynamic temperature control can be used to localize and characterize the resistive faults created by such thermally induced cracks. The EOTPR technique provides quick, reliable, and accurate results, and it allows automatic probing that can be used to generate defect maps for further root cause analysis. The approach demonstrated in this paper shows the significant potential of EOTPR in soft failure characterization and in failure and reliability analysis.

Passive voltage contrast (PVC) is a well-known fault isolation technique in differentiating contrast at via/metal/contact levels while focused ion beam (FIB) is a destructive technique specifically used for cross sectioning once a defect is identified. In this study, we highlight a combination technique of PVC and progressive FIB milling on advanced node fin field-effect transistor (FinFET) for root cause analysis. This combo technique is useful when applied on high-density static random access memory (SRAM) structure, especially when it is difficult to view the defect from top-down inspection. In this paper, we create a FA flow chart and FIB deposition/milling recipe for SRAM failure and successfully apply them to three case studies.

Photon Emission Microscopy (PEM) analysis is one of the most common used FA techniques to identify the root cause of failures within ATPG scan logic due to its ease of setup and less invasive nature. While conducting photon emissions, the device is made to operate in the fail mode by running a production test vector to look for anomalous emissions or hot spots that could narrow down the area of interest (AOI) for subsequent Physical Failure Analysis (PFA). However, if there is no clue from emission analysis in the case of a hard failure with no sensitivity to voltage, frequency, or temperature, FA debug will be challenging. This paper shows how PEM analysis success may be further improved through logic state circuit study using a DFT ATPG diagnostic platform. Logic state truth table and its relative test pattern will be built based on the diagnostic data using in-house scripts, and the test program can then be changed to the required condition of the circuitry. With the altered logic state, new emission data can be collected, which could potentially reveal new clues to the investigation.