Novel sample preparation techniques have been developed for Three-Dimensional Heterogeneously Integrated (3DHI) devices to enable precise failure analysis while protecting adjacent components. Traditional grinding and polishing methods risk damaging surrounding areas when tool bits extend beyond the target region. Using the VarioMill system's high-precision stages (±1µm accuracy), we introduce three key innovations: a helical grinding approach for accessing die centers, an extended tool bit technique for processing rectangular corners, and enhanced polishing protocols. These methods allow for targeted sample preparation of individual dies or specific die regions while completely preserving adjacent components. The techniques are particularly valuable for complex, densely packed 3DHI devices where conventional preparation methods pose significant risks of collateral damage.

Cross-sectional analysis plays a crucial role in failure analysis for the identification of root causes associated with implants or junction profiles. Traditionally, this step involves junction staining. Recently, Electron Beam Induced Current (EBIC) analysis has emerged as a valuable alternative, offering the key advantage of visualizing various implantations and junction profiles through non-chemical means. This paper presents an innovative sample preparation technique for cross-sectional EBIC analysis, incorporating an additional step of FIB (Focused Ion Beam) grooving at the target site before cross-sectional polishing. Unlike conventional methods that involve laborious and time-consuming fine cross-sectional polishing, our approach enhances precision and efficiency. With the elimination of the need for extensive polishing, direct access to the target is achieved after rough polishing, thereby expediting the analytical process.

The role of scanning transmission electron microscopy (STEM) in failure analysis has been growing since the introduction of advanced technology nodes (10-nm and beyond), in which transistors (FinFET and nanosheets) have become much smaller and more complex. Four-dimensional scanning transmission electron microscopy (4D-STEM) is a new electron diffraction technique that expands conventional STEM imaging and EDX mapping to enable phase and orientation mapping of crystalline and amorphous phases in deposited thin films at the nanometer resolution. The enhancement of electron diffraction data by beam precession is then fundamental for higher accuracy and precision, especially in the case of strain measurements. The power of precession-assisted 4D-STEM analysis is demonstrated using the example of Germanium separation from within a Ge-rich GeSbTe layer in a phase memory device and with the example of tensile and compressive strain in a Samsung 5-nm technology node. These advanced electron diffraction measurements are now accessible to a broad range of users in routine analytical procedures due to unprecedented high levels of automation and synchronization in the new analytical STEM instrument, TESCAN TENSOR.

The rapid development of advanced packaging technologies for high-performance computing (HPC) applications poses significant challenges for sample preparation methodologies. Conventional techniques are often insufficient to cope with the complex architectures and heterogeneous materials of modern packages, such as COWOS (Chip-on-Wafer-on-Substrate) and 3D structures. In this paper, we present a novel approach for sample preparation that leverages precision CNC (Computer Numerical Control) milling and selective MIP plasma etch. These methods enable precise and selective removal of unwanted material, while preserving the integrity of the target region of interest. We demonstrate the effectiveness of our approach on various advanced packages and show how it facilitates the failure analysis tasks for HPC chips.

As semiconductor devices continue to decrease in size and pitch, demands for accurate microstructural analysis have increased to enable downward scaling. Critical dimension (CD) metrology is key to delivering process insights, but at such scales, rigorous metrology analysis providing high precision data may lack desired throughput. CD measurement using the scanning electron microscope (SEM) is a widely used technique, however, to acquire large area SEM images with high precision, multiple image stitching is currently required. In this paper, a new method for precise and efficient metrology analysis is introduced. This study demonstrates that large area imaging with ultra-high pixel resolution can deliver better throughput while maintaining the same level of precision that can be achieved by the traditional method.

This paper describes the development and implementation of a TEM-based measurement procedure and shows how it is used to determine the verticality or etching angle of channel holes in V-NAND flash with more than 200 layers of memory cells. Despite the high aspect ratio of the region of interest, the method can resolve offsets down to a few nm. Such precision is critical, as the paper explains, because the radius and thus electrical characteristics of each memory cell is determined by the etching angle.