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1-19 of 19
Failure mode and effects analysis
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Proceedings Papers
ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 43-45, November 5–9, 2017,
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Through Silicon Via (TSV) Package (PKG) technology that forms a 3D stack with chip to chip or wafer to wafer contact, uses a variety of wet chemicals unlike conventional package technology. Therefore, new kinds of defects related to the wet chemical occur. In this a new failure mode of disappeared Al pad will be presented, a problem came up to disappear Al pad, which served as the fiducial key during the metal residue removal process after forming the TSV PKG front bump, the mechanism of disappearance of Al pad was investigated. Through chemical analysis of process and equipment, we found that Cu etchant (including H3PO4) can damage for Al pad. The process simulation demonstrated that Al pad actually disappeared. Therefore, it confirmed that it needs to be removed through sufficient rinsing time after applying the wet chemical applied to the TSV PKG process. As a result we solved problem through modified equipment and increased rinsing time.
Proceedings Papers
ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 631-634, November 5–9, 2017,
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This paper presents the failure analysis on a 1.5m flex harness for a space flight instrument that exhibited two failure modes: global isolation resistances between all adjacent traces measured tens of milliohm and lower resistance on the order of 1 kiloohm was observed on several pins. It shows a novel method using a temperature controlled air stream while monitoring isolation resistance to identify a general area of interest of a low isolation resistance failure. The paper explains how isolation resistance measurements were taken and details the steps taken in both destructive and non-destructive analyses. In theory, infrared hotspot could have been completed along the length of the flex harness to locate the failure site. However, with a field of view of approximately 5 x 5 cm, this technique would have been time prohibitive.
Proceedings Papers
ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 144-148, November 3–7, 2013,
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Test structure characterization plays a predominant role throughout the entire development cycle of a product. They are used to understand the process windows and also help to monitor the health of line (HOL). One of the key principles in successfully monitoring the HOL is to establish passing and failing electrical criteria to various test structures. This paper shows electrical and physical characterization of one such test structure. Further, a novel way of establishing electrical signatures to specific defect fail mode finger prints for early identification and monitoring of process-related defects is proposed.
Proceedings Papers
ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 456-462, November 3–7, 2013,
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Gate-to-drain contact short issue in floating gate memory has been studied. Two cases will be discussed, floating-gate to drain contact short, and control-gate to drain contact short, both caused by leakage bridge defect. The abnormal electrical device characteristic combined with modeling gives further insight into the failure mode. Nano-prober measurement results not only provide an evidence of short-contact issue but also measures the current behaviors between drain and gate in floating gate configuration. These results help to predict the defect location and successfully monitor the bridge-failure through electrical analysis.
Proceedings Papers
ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 582-586, November 3–7, 2013,
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This paper presents the successful use of the novel inline product-like logic vehicle (PATO) during the last technology development phases of IBM's 22nm SOI technology node. It provides information on the sequential PATO inline test flow, commonality analysis procedure, and commonality signature trending. The paper presents examples of systematic defects uniquely captured by the product-like back end of the line layout. Moreover, this complex logic vehicle also uncovered a rich Pareto of more than 20 types of systematic and random defect mechanisms across the front end of the line, the middle end of the line, and the back end of the line. And more importantly, the non-defect found rate was kept below 20%. This achievement was possible by: leveraging high volume inline test ATPG scan fail data through the novel commonality analysis approach; and selecting the highest ATPG confidence defects representing a known commonality signature to physical failure analysis.
Proceedings Papers
ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 118-122, November 11–15, 2012,
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This paper demonstrated the use of curve fitting method on device transfer characteristic curve for device carrier mobility analysis and failure mechanism verification. In the content, a systematic device characterization was performed to identify device failure mode and failure site. Based on physical observations and electrical results, a device gate oxide boron penetration failure mechanism and an unexpected subtle p-type dopant at p-MOS device channel area was conjectured. However, this unexpected p-type dopant was successfully proved by subsequent carrier mobility analysis results, and the gate oxide boron penetration failure mechanism was accordingly verified.
Proceedings Papers
ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 596-600, November 11–15, 2012,
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Cold temperature failures are often difficult to resolve, especially those at extreme low levels (< -40°C). Momentary application of chill spray can confirm the failure mode, but is impractical during photoemission microscopy (PEM), laser scanning microscopy (LSM), and multiple point microprobing. This paper will examine relatively low-cost cold temperature systems that can hold samples at steady state extreme low temperatures and describe a case study where a cold temperature stage was combined with LSM soft defect localization (SDL) to rapidly identify the cause of a complex cold temperature failure mechanism.
Proceedings Papers
ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 54-57, November 14–18, 2010,
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High contact resistance can be caused by moisture absorption in low phosphorus content BPTEOS. Moisture diffused through the TiN glue layer is absorbed by the BPTEOS during subsequent thermal processes resulting in increased contact resistance. This failure mode was studied by combining different failure analysis methods and was confirmed by duplication on experimental wafers.
Proceedings Papers
ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 449-456, November 14–18, 2010,
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Schottky diodes are semiconductor switching devices with low forward voltage drops and very fast switching speeds. This paper provides an overview of the common failure modes in Schottky diodes and corresponding failure mechanisms associated with each failure mode. Results of material level evaluation on diodes and packages as well as manufacturing and assembly processes are analyzed to identify a set of possible failure sites with associated failure modes, mechanisms, and causes. A case study is then presented to illustrate the application of a systematic FMMEA methodology to the analysis of a specific failure in a Schottky diode package.
Proceedings Papers
ISTFA2009, ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis, 81-87, November 15–19, 2009,
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The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.
Proceedings Papers
ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 344-348, November 2–6, 2008,
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The flash considered for failure analysis in this paper is a non volatile memory with a NOR architecture in the array and a stacked gate for the bit cell. The flash failure was from data gain reported from various stages and at different temperatures after leaving the wafer fabrication. The failure can be single bit failure (SBF) or multiple bit failure (MBF). The FA process is comprised of two steps termed electrical failure analysis (EFA) and physical failure analysis (PFA). This paper discusses the method to differentiate failure modes and the efforts of fault isolation. Micro probing and nano probe characterization were important in the understanding of the failure mechanism. As seen in the EFA/PFA section, the reported SBF/MBF failures were actually due to a defect in the Mux and not at the bit cell.
Proceedings Papers
ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 354-362, November 2–6, 2008,
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To be better prepared to use laser based failure isolation techniques on field failures of complex integrated circuits, simple test structures without any failures can be used to study Optical Beam Induced Resistance Change (OBIRCH) results. In this article, four case studies are presented on the following test structures: metal strap, contact string, VIA string, and comb test structure. Several experiments were done to investigate why an OBIRCH image was seen in certain areas of a VIA string and not in others. One experiment showed the OBRICH variation was not related to the cooling and heating effects of the topology, or laser beam focusing. A 4 point probe resistance measurement and cross-sectional views correlated with the OBIRCH results and proved OBIRCH was able to detect a variation in VIA fabrication.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 264-267, November 12–16, 2006,
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This paper presents a novel deductive methodology, which is accomplished by applying difference analysis to nano-probing technique. In order to prove the novel methodology, the specimens with 90nm process and soft failures were chosen for the experiment. The objective is to overcome the difficulty in detecting non-visual, erratic, and complex failure modes. And the original idea of this deductive method is based on the complete measurement of electrical characteristic by nano-probing and difference analysis. The capability to distinguish erratic and invisible defect was proven, even when the compound and complicated failure mode resulted in a puzzling characteristic.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 276-278, November 12–16, 2006,
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As semiconductor technology advances from one node to the next, fabrication also becomes increasingly challenging to ramp up production with the most desirable yield and reliable product in a timely manner. At an advanced technology node such as 65nm, the interaction between product design, process margin, and process equipment continues to limit the product yield and reliability performance. Traditional methods, which usually rely on sequential feedback of each experimental lot, require too many learning cycles to achieve target performance, yield, and reliability levels. This paper describes a methodology that potentially accelerates the progression of identifying process and product-design interactions and marginalities during the development stage. It demonstrates the successful application of a failure mode effect analysis design design-of-experiments reticle for extracting process-design interaction information. This approach provides insights to early learning cycles in achieving accelerated critical learning for yield and reliability improvements.
Proceedings Papers
ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 140-144, November 6–10, 2005,
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Printed Circuit Board (PCB) assemblies are moving toward lead-free (LF) alloys and away from the traditional Sn-Pb alloy [1]. This change is creating new and unique failure modes as the process adapts to accommodate the higher temperatures of the new process [2]. In addition, mis-processed lots are more likely due to the complexity of assembling a mix of Sn-Pb and leadfree solders, components, PCBs, solder pastes, and fluxes. This case study helps to highlight the challenge and provides an example of what can happen, how to detect it, and how the defects can cause reliability failures.
Proceedings Papers
ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 125-130, November 2–6, 2003,
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This paper correlates the reseat failure rates of a PCI option card to the use of thin gold plating across the contact fingers. This failure mechanism results in increased contact resistance and is often misdiagnosed due to its intermittent failure mode. As many new manufactures appear in Asia, the push for global competitiveness to achieve high volume and reduced costs can result in insufficient plating finishes being applied to the contact fingers. Compounding this problem is the fact the many companies use multiple raw board suppliers to meet these volume requirements. Many times the end user of the option card is unaware of the wide variation in contact plating thickness that may be present from one raw board source to another. Intermittent failures are one of the most common defects experienced in high volume assembly. Unless properly diagnosed, these failures can be attributed to finger debris, rework flux, solder paste contamination and even connector related issues. The typical fix, whether approved by the process or not, is for the manufacturing assembler to reseat all of the option cards and memory into the Motherboard connector sockets. Unless the proper troubleshooting approach is followed, isolating the true root cause of the actual failure can be missed. The difficulty in identifying the reseat problem is compounded by the fact that the failures are often intermittent in nature. While reseating may temporarily achieve sufficient mating between the board’s contact fingers and the connector contacts, it provides no long term fix. These unnecessary reseats also reduce the long-term durability of already thin plating affecting customer satisfaction and warranty costs. In the paper, we will expand on the theory behind the XRF plating thickness testing, including: • System theory • Test calibration • Part orientation • Test measurement criteria Additional analysis of metallurgical cross-sectioning was performed to correlate the XRF test readings to the actual plated layers. The measurements were completed by use of a SEM (Scanning Electron Microscopy).
Proceedings Papers
ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 209-214, November 2–6, 2003,
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Via in pad PCB (Printed Circuit board) technology for passive components such as chip capacitors and resistors, provides the potential for improved signal routing density and reduced PCB area. Because of these improvements there is the potential for PCB cost reduction as well as gains in electrical performance through reduced impedance and inductance. However, not long after the implementation, double digit unit failures for solder joint electrical opens due to capacitor “tombstoning” began to occur. Failure modes included via fill material (solder mask) protrusion from the via as well as “out gassing” and related “tombstoning.” This failure analysis involved investigating a strong dependence on PCB supplier and, less obviously, manufacturing site. Other factors evaluated included via fill material, drill size, via fill thermal history and via fill amount or fill percent. The factor most implicated was incomplete cure of the via fill material. Previous thermal gravimetric analysis methods to determine level of polymerization or cure did not provide an ability to measure and demonstrate via fill cure level in small selected areas or its link to the failures. As a result, there was a metrology approach developed to establish this link and root-cause the failures in the field, which was based on microhardness techniques and noncontact via fill measuring metrologies.
Proceedings Papers
ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 272-277, November 2–6, 2003,
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The correlation between electrical characteristics and failure modes in some common cases of ESD protection circuitry is described. The investigation is based on experimental results obtained during the qualification of highly integrated CPUs and chipsets manufactured by 0.18 µm CMOS technology. The implementation of these data during qualification of 0.13 µm CMOS products allowed the decrease of qualification throughput time (TPT), and, in some cases, reduction of FA efforts. Some process related and designs related ESD concerns are discussed herein.
Proceedings Papers
ISTFA1999, ISTFA 1999: Conference Proceedings from the 25th International Symposium for Testing and Failure Analysis, 203-207, November 14–18, 1999,
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FMECA tools must be included into the designers tools suite in order to support the new vision for a concurrent engineering environment. To support this new vision we introduce a major enhancement to the Failure Mode Effects and Criticality Analysis (FMECA) to provide a more accurate, simpler, accessible and frequently used computerized analysis tool. We introduce new terminology to enhance the well-known standards, while assuring their full support. Using the new terminology, functional trees become very similar to the project trees and can be drawn as block diagrams, e.g. the time spent on constructing the functional trees is reduced by factors.