Continued technology scaling has led to exposure of many ‘weak-points’ in the designs fabricated in some of the most advanced technology nodes. Weak-points are certain layout patterns which are found to be sensitive to process non-idealities and have a higher tendency to cause defects. They may be coded in the form of Pattern Matching (PM) rules and included within the Design for Manufacturability Guidelines (DFMGs) to ensure product manufacturability. Often, during Integrated Circuit (IC) design, a trade-off is made between meeting performance specifications and complying with DFMGs. As a result, designs may reach the foundry with some DFMG violations. Fixing such violations generally causes a ‘ripple effect’ where one change requires many changes in other metal layers, making the process tedious. Therefore, providing a ranked list of guidelines to the designers helps them in assessing the criticality of violations, prioritizing, and fixing them accordingly. Past research suggests using diagnosis data to determine the impact of DFMG violations. However, this is a reactive approach wherein DFMGs are ranked only based on their hard-defect causing nature. To make the ranking process more robust, we propose a proactive silicon validation based approach which not only considers the yield loss due to hard-defects but also takes into account the parametric and reliability degradation caused by DFMG violations. We evaluate the effectiveness of the proposed methodology through on-silicon experiments on an advanced Fully-Depleted Silicon-On-Insulator (FD-SOI) technology node.

Several product lots were found to suffer from data retention failures in OTP (one time program) devices. PFA (physical failure analysis) was performed on these devices, but nothing abnormal was observed. Cross-sectional TEM (transmission electron microscopy) revealed no physical defects or abnormal CDs (critical dimensions). In order to isolate the failed layer or location, electrical analysis was conducted. Several electrical simulation experiments, designed to test the data retention properties of OTP devices, were preformed. Meilke's method [1] was also used to differentiate between mobile ion contamination and charge trap centers. Besides Meilke's method, a new electrical analysis method was used to verify the analysis results. The results of our analysis suggests that SiN charge trap centers are the root cause for the data retention failures, and the ratio of Si/N is the key to charge trap center formation. Auger analysis was used to physically check the Si/N ratio of OTP devices. The results support our hypothesis. Subsequent DOE (Design Of Experiment) experiments also confirm our analysis results. Key Words: OTP, data retention, Non-visible defect, AFP, charge trap center, mobile ion.

An aggressive yield improvement program that was undertaken by the engineering teams has culminated in the works reported in this paper. The power down current (Idd_Pd) was one of the major failure modes recorded for CMOS ICs. In essence, any improvement made on the Idd_Pd test yield will result in substantial gain in terms of cost and production capacity. A taskforce to resolve high fallouts for the Idd_Pd was then formed back in the year 2004. This taskforce comprised of members from various engineering teams, for instance, Manufacturing, IC Design, Materials and Failure Analysis (FA). The length of investigation to resolve the complex high Idd_Pd failures had spanned over a period of a year. The team had devised a comprehensive sets of DOEs (Design of Experiments) which were conducted at various contract manufacturing facilities where the ICs were packaged. Results obtained from these DOEs had conclusively pointed to molded materials as the major factor contributing to high Idd_Pd yield loss. Armed with this vital information, FA had performed an indepth electrical diagnosis as well as physical analysis on the molded materials. The analysis results had confirmed contamination of the molding materials by conductive carbonized resin as the cause of high leakage current in ICs. Likewise, the material supplier had found minute contamination in the resin melt. In essence, Idd_Pds that were measured in the range of tens of microamps to thousands of microamps in ICs could be largely attributed to leakages caused by carbonized resin in the molded materials.

As semiconductor technology advances from one node to the next, fabrication also becomes increasingly challenging to ramp up production with the most desirable yield and reliable product in a timely manner. At an advanced technology node such as 65nm, the interaction between product design, process margin, and process equipment continues to limit the product yield and reliability performance. Traditional methods, which usually rely on sequential feedback of each experimental lot, require too many learning cycles to achieve target performance, yield, and reliability levels. This paper describes a methodology that potentially accelerates the progression of identifying process and product-design interactions and marginalities during the development stage. It demonstrates the successful application of a failure mode effect analysis design design-of-experiments reticle for extracting process-design interaction information. This approach provides insights to early learning cycles in achieving accelerated critical learning for yield and reliability improvements.