Novel sample preparation techniques have been developed for Three-Dimensional Heterogeneously Integrated (3DHI) devices to enable precise failure analysis while protecting adjacent components. Traditional grinding and polishing methods risk damaging surrounding areas when tool bits extend beyond the target region. Using the VarioMill system's high-precision stages (±1µm accuracy), we introduce three key innovations: a helical grinding approach for accessing die centers, an extended tool bit technique for processing rectangular corners, and enhanced polishing protocols. These methods allow for targeted sample preparation of individual dies or specific die regions while completely preserving adjacent components. The techniques are particularly valuable for complex, densely packed 3DHI devices where conventional preparation methods pose significant risks of collateral damage.

Integrated circuit (IC) delayering is highly subjective, as operators must make process decisions based on minute details observed in optical images of the ICs. Process decisions have a strong influence on the quality of the final sample, with the result being highly dependent on an operator’s technique, skill, and experience. However, end point detection, process development, and in-process feedback all benefit from a quantitative method to evaluate results. To this end, a quality metric for IC delayering based solely on optical images has been developed. The optical images are processed into CIE-Lab color space, candidate zones are established, and color homogeneity both within and among these zones is calculated, which contribute to a final die quality score. The work done in this study takes a significant step forward in quantifying IC delayering results, which is critical for improving repeatability, reproducibility, and developing automation frameworks in these workflows.

Cross-sectional analysis plays a crucial role in failure analysis for the identification of root causes associated with implants or junction profiles. Traditionally, this step involves junction staining. Recently, Electron Beam Induced Current (EBIC) analysis has emerged as a valuable alternative, offering the key advantage of visualizing various implantations and junction profiles through non-chemical means. This paper presents an innovative sample preparation technique for cross-sectional EBIC analysis, incorporating an additional step of FIB (Focused Ion Beam) grooving at the target site before cross-sectional polishing. Unlike conventional methods that involve laborious and time-consuming fine cross-sectional polishing, our approach enhances precision and efficiency. With the elimination of the need for extensive polishing, direct access to the target is achieved after rough polishing, thereby expediting the analytical process.

The role of scanning transmission electron microscopy (STEM) in failure analysis has been growing since the introduction of advanced technology nodes (10-nm and beyond), in which transistors (FinFET and nanosheets) have become much smaller and more complex. Four-dimensional scanning transmission electron microscopy (4D-STEM) is a new electron diffraction technique that expands conventional STEM imaging and EDX mapping to enable phase and orientation mapping of crystalline and amorphous phases in deposited thin films at the nanometer resolution. The enhancement of electron diffraction data by beam precession is then fundamental for higher accuracy and precision, especially in the case of strain measurements. The power of precession-assisted 4D-STEM analysis is demonstrated using the example of Germanium separation from within a Ge-rich GeSbTe layer in a phase memory device and with the example of tensile and compressive strain in a Samsung 5-nm technology node. These advanced electron diffraction measurements are now accessible to a broad range of users in routine analytical procedures due to unprecedented high levels of automation and synchronization in the new analytical STEM instrument, TESCAN TENSOR.

The rapid development of advanced packaging technologies for high-performance computing (HPC) applications poses significant challenges for sample preparation methodologies. Conventional techniques are often insufficient to cope with the complex architectures and heterogeneous materials of modern packages, such as COWOS (Chip-on-Wafer-on-Substrate) and 3D structures. In this paper, we present a novel approach for sample preparation that leverages precision CNC (Computer Numerical Control) milling and selective MIP plasma etch. These methods enable precise and selective removal of unwanted material, while preserving the integrity of the target region of interest. We demonstrate the effectiveness of our approach on various advanced packages and show how it facilitates the failure analysis tasks for HPC chips.

As semiconductor devices continue to decrease in size and pitch, demands for accurate microstructural analysis have increased to enable downward scaling. Critical dimension (CD) metrology is key to delivering process insights, but at such scales, rigorous metrology analysis providing high precision data may lack desired throughput. CD measurement using the scanning electron microscope (SEM) is a widely used technique, however, to acquire large area SEM images with high precision, multiple image stitching is currently required. In this paper, a new method for precise and efficient metrology analysis is introduced. This study demonstrates that large area imaging with ultra-high pixel resolution can deliver better throughput while maintaining the same level of precision that can be achieved by the traditional method.

This paper presents advanced workflows that combine 3D Xray microscopy (XRM), nanoscale tomography, and electron microscopy to generate a detailed visualization of the interior of electronic devices and assemblies to enable the study of internal components for failure analysis (FA). Newly developed techniques such as the integration of deep-learning (DL) based algorithms for 3D image reconstruction are also discussed in this article. In addition, a DL-based tool (called DeepScout) is introduced that uses high-resolution 3D XRM datasets as training data for lower-resolution, larger field-of-view datasets and scales larger-volume data using a neural network model. Ultimately, these workflows can be run independently or complementary to other multiscale correlative microscopy evaluations, e.g., electron microscopy, and will provide valuable insights into the inner workings of electronic packages and integrated circuits at multiple length scales, from macroscopic features on electronic devices (i.e., hundreds of mm) to microscopic details in electronic components (in the tens of nm). Understanding advanced electronic systems through X-ray imaging and electron microscopy, and possibly complemented with some additional correlative microscopy investigations, can speed development time, increase cost efficiency, and simplify FA and quality inspection of printed circuit boards (PCBs) and electronic devices assembled with new emerging technologies.

This presentation provides an overview of lock-in thermography and its application in semiconductor failure analysis. It begins with a review of direct thermal imaging, IR transmission and detection, and the fundamentals of lock-in measurements. It compares and contrasts steady-state IR imaging with lock-in thermography and shows how lock-in frequency and the shape of the excitation signal can be varied to increase signal-to-noise ratio and reduce acquisition time, thereby exposing a wider range of defects. It also presents several case studies in which lock-in thermography is used to diagnose shorts and hot spots in packaged devices, electronic systems, and 3D assemblies.

This presentation shows how transmission electron microscopy (TEM) is used in semiconductor failure analysis to locate and identify defects based on their physical and elemental characteristics. It covers sample preparation methods for planar, cross-sectional, and elemental analysis, reviews the capabilities of different illumination and imaging modes, and shows how beam-specimen interactions are employed in energy dispersive (EDS) and electron energy loss spectroscopy (EELS). It describes the various ways transmission electron microscopes can be configured for elemental analysis and mapping and reviews the advantages of scanning TEM (STEM) approaches. It also provides an introduction to energy-filtered TEM (EFTEM) and how it compares with other TEM imaging techniques.

This presentation provides an introduction to atomic force microscopy (AFM) and its many uses in semiconductor failure analysis. It provides examples showing how AFM is used to obtain information on electric fields, surface potential, current, resistance, capacitance, impedance, carrier concentration, mechanical contact (height and energy dissipation), temperature, and composition. It also addresses a number of related issues including the use of external stimuli, sample preparation requirements, and probe tip selection.

This presentation covers the challenges associated with IC package inspection and shows how two nondestructive techniques, scanning acoustic microscopy and X-ray imaging, are being used to locate and identify a wide range of defects, particularly those in 3D packages and multilayer boards. It reviews the basic principles of scanning acoustic microscopy (SAM), X-ray imaging, and 3D X-ray tomography and the factors that affect image resolution and depth. It demonstrates the current capabilities of each method along with different approaches for improving resolution, contrast, and measurement time.

This presentation is an introduction to machine learning techniques and their application in semiconductor failure analysis. The presentation compares and contrasts supervised, unsupervised, and reinforcement learning methods, particularly for neural networks, and lays out the steps of a typical machine learning workflow, including the assessment of data quality. It also presents case studies in which machine learning is used to detect and classify circuit board defects and analyze scanning acoustic microscopy (SAM) data for blind source separation.

This paper evaluates several approaches for automating the identification and classification of logos on printed circuit boards (PCBs) and ICs. It assesses machine learning and computer vision techniques as well as neural network algorithms. It explains how the authors created a representative dataset for machine learning by collecting variants of logos from PCBs and by applying data augmentation techniques. Besides addressing the challenges of image classification, the paper presents the results of experiments using Random Forest classifiers, Bag of Visual Words (BoVW) based on SIFT and ORB Fully Connected Neural Networks (FCN), and Convolutional Neural Network (CNN) architectures. It also discusses edge cases where the algorithms are prone to fail and where potential opportunities exist for future work in PCB logo identification, component authentication, and counterfeit detection. The code for the algorithms along with the dataset incorporating 18 classes of logos and more than 14,000 images is available at this link: https://www.trusthub.org/#/data .

This article describes a method that combines Analog Signature Analysis (ASA) with IR based Direct Current Injection (IRDCI) for printed circuit board assembly failure analysis. The integration of ASA extends the diagnostic capability of IRDCI from shorted power rails to any measurement location that shows signature differences. It also facilitates the detection of electrical breakdown or degradation without having to remove suspected faulty components from the board.

There are several variants of artificial intelligence (AI) hardware structures that are under study by the semiconductor industry for potential use in complementary metal–oxide–semiconductor (CMOS) designs. This paper discusses some of the failure analysis challenges that have appeared in discrete test structures and test arrays developed as part of an exploratory phase-change memory (PCM) program at IBM's Albany AI Hardware Research Center.

This paper describes a project to develop and deploy a systematic screening methodology involving computed tomography (CT) to inspect a set of electromagnetic interference (EMI) filter components for a spacecraft application. The goal was to deploy the nondestructive CT test to replace the destructive test method typically deployed for such components. The paper describes the development of test criteria, fixturing, inspection process, and data analysis, including quantitative image analysis of voids and cracks. The initial results indicated that the parts would not pass the requirements established in the test design. A waiver was written to the project clarifying that if the parts were to be used in the assembly, they should be considered as simple conductors with EMI filtering capability viewed as an added benefit rather than a guaranteed design requirement.

This paper discusses the basic physics of scanning acoustic microscopy, the counterfeit features it can detect, and how it compares with other screening methods. Unlike traditional optical inspection and IR and X-ray techniques, SAM can identify recycled and remarked chips by exposing ghost markings, fill material differences, delaminations from excessive handling, and popcorn fractures caused by trapped moisture. The paper presents several examples along with detailed images of these telltale signs of semiconductor counterfeiting. It also discusses the potential of developing an automated solution for detecting counterfeits on a large scale.

PCB assurance currently relies on manual physical inspection, which is time consuming, expensive and prone to error. In this study, we propose a novel automated segmentation algorithm to detect and isolate PCB components called EC-Seg. Component segmentation and localization is a vital preprocessing step in the automation of component identification and authentication as well as the detection of logos and text markings. As test results indicate, EC-Seg is an efficient solution to automate quality assurance toolchains and also aid bill-of-material (BoM) extraction in PCBs. It also has the potential to be used as a region proposal algorithm for object detection networks and to facilitate sensor fusion involving artifact removal in PCB X-ray tomography.

Static random access memory (SRAM) can occupy up to 90% of the die surface in a microprocessor and is often laid out with even more aggressive design rules than logic circuitry, which makes it more prone to manufacturing defects and more sensitive to process variations. As a result, SRAM is often chosen to be the process qualification vehicle during technology development and the yield learning vehicle during product manufacturing. Consequently, fast and accurate analysis of SRAM failure is critical to success on many levels. In this paper, we present a defect identification method that combines design for test (DFT) features, direct bitcell access (DBA), and nondestructive fault isolation techniques. With examples and case studies, it is shown how the approach makes use of electrical failure analysis data to greatly reduce the cycle time of root cause identification in the early stages of new technology development.

The automation of TEM imaging and lamella preparation using focused ion beam (FIB) technology has gained significant momentum, particularly in the development of microprocessors. A key requirement of automating TEM sample preparation is ensuring consistent thickness control and accurate targeting of features of interest in the ultra-thin lamella. This work examines the factors that impact both metrics. It explains how FIB pattern calibration requires milling to be divided into steps to minimize the effects of drift, how the height of the protective cap on the ion-beam tip influences sample thickness, and how FIB aperture erosion has little impact on lamella thickness until it reaches a certain point where the lamella profile cannot be reliably maintained. It was also found that the tail of the ion beam remains invariant during aperture degradation in the operable range and that it plays a prominent role in determining the cross-sectional thickness of the TEM lamella.