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Proceedings Papers
ISTFA2024, ISTFA 2024: Tutorial Presentations from the 50th International Symposium for Testing and Failure Analysis, i1-i57, October 28–November 1, 2024,
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Presentation slides for the ISTFA 2024 Tutorial session “Electron-Beam Probing of Modern Integrated Circuits: Moving Forward while Borrowing from the Past.”
Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 5-8, October 28–November 1, 2024,
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In this paper, we propose an advanced failure analysis method for specifying the location of gate-related fails in the High-k Metal Gate (HKMG) MOSFET. The test sample for this experiment is the sub-15nm technology DRAM (Dynamic Random Access Memory) which consists of high speed HKMG transistors. In terms of HKMG transistors, the modification of gate materials and process schemes provoke the various gate related failures in DRAM which makes it more difficult to examine the sample with conventional analyzing methods. So, IDD3P measurement methods along with dynamic Hot Electron Analyzer (HEA) were employed as an advanced fault localization method. IDD3P measurement data provides word-line (WL) dependent failure types which distinguishes the gate-related failures from other irrelevant failures. From the dynamic HEA with the MAGNUM tester, the accurate failure sites can be obtained. Newly combined two analytical methods that we present in this paper are effective in localizing the failure sites more accurate than previously suggested methods.
Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 58-69, October 28–November 1, 2024,
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One of the foremost challenges in the field of SiC MOSFET failure analysis is the effect of thermally modified mold compound on the decapsulation process. The extended total etch time that thermal modification imposes on the process of wet chemical decapsulation has created a niche for new techniques to fill. This paper focuses on use cases for the JIACO microwave-induced plasma (MIP) etching system and how to best optimize the tool’s settings to facilitate time-efficient decapsulations. The words and data that follow aim to present what has been determined to be a successful alternative for the decapsulation of thermally modified Si and SiC power devices when wet etches prove to be ineffective.
Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 74-78, October 28–November 1, 2024,
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Analyzing scan chain failures is challenging without dedicated test hardware. Traditional solutions like ATE testers and compact diagnosis tools have significant drawbacks: they're expensive, require complex hardware customization and proprietary software licenses, and need substantial lab space. This paper presents a cost-effective alternative: a portable, flexible, and fully customizable bench-top scan chain testing system that easily integrates with fault isolation tools. Using an off-the-shelf embedded development tool, we replicated the complete scan chain testing process—from pattern generation to test vector transmission/reception and results comparison. The system reduces costs by approximately 200-fold compared to traditional solutions. We validated our approach by analyzing a device with marginal and frequency-dependent stuck-at-scan failures. Using DALS (Dynamic Analog Laser Stimulation), we successfully localized the defect and confirmed it through mechanical delayering, FIB cross-sectioning, and SEM imaging.
Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 161-164, October 28–November 1, 2024,
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A successful failure analysis not only depends on extensive electrical and physical fault isolation by using all the advanced FA tools to narrow down the possible failure site, but also relies on actual physical defect findings. For advanced IC devices with technologies approaching sub-10nm and more than 10 layers of metallization built in ultra-low k materials, finding convincing physical defects becomes increasingly challenging. Backside deprocessing to reveal the physical defects at the active circuit layers and interconnect layers have been mostly done with KOH or TMAH as bulk Si etching chemicals, and some successful results have been published in the literatures. However, some challenges are also reported using these chemicals to achieve satisfactory results. In this paper, an improved backside deprocessing technique will be discussed using a special bulk Si etching chemical, choline hydroxide, to successfully reveal the physical defects on advanced IC devices. The new technique showed advantages over the existing techniques with more predictable and reliable results for backside deprocessing work. Two case studies will also be shared to demonstrate how this improved technique has been utilized to successfully reveal the physical damage at transistor gate level on the advanced MCU devices.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 34-40, November 12–16, 2023,
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Lead-free solder joints tend to be more susceptible to brittle fracture, and thus susceptible to drop-damage. Drop testing of handheld ultrasound devices revealed broken solder joints on a large inductor component. Analysis of the cracks showed a dual intermetallic compound (IMC) layer of Ni 3 Sn 4 (closest to the nickel) and (Ni,Cu) 6 Sn 5 , with the crack occurring in between the two layers. The inductor had a tinned nickel lead finish; the solder was SAC305 (a common lead-free solder comprising Sn, Ag, and Cu); and the printed circuit board (PCB) had a standard copper finish. The failure occurred very soon after manufacture and had not been enhanced by temperature cycling or aging, but it was not a time-zero failure: mechanical shocks from drops were required to propagate the crack through the joint fully. Strain measurements did not find any large strains after reflow and assembly, and no other components on the board showed cracking. There was no cracking observed at the PCB (Cu) side of the solder joint. The solution ultimately was to redesign the board, replacing the large single component with several smaller ones.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 41-44, November 12–16, 2023,
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Laser voltage imaging techniques are widely used in failure analysis for detecting defects in digital circuitry. In case of scan chain failures that are substantially static, this is really the most suitable application. In this paper we explore and demonstrate the potential of this method for characterizing transition delay failures in combinatorial logic, through the real-time measurement of the behaviour of each transistor in the cell.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 45-53, November 12–16, 2023,
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Integrated capacitors use metal plates such as in Metal-Insulator-Metal (MIM) and Metal-Oxide-Metal (MOM) capacitors while Polysilicon and Silicon (Si) substrate for metal-oxide-semiconductor (MOS) capacitors. Three major challenges and solutions were discussed in this technical paper. First, the failure site localization of a subtle defect in the capacitor plates. To determine the specific location of the defect site, Electron Beam Induced Current (EBIC) analysis was performed while the part was biased using a nano-probe set-up under Scanning Electron Microscopy (SEM) environment. Second, Failure Mechanism contentions between Electrically Induced Physical Damage (EIPD) or Fabrication process defect particularly, for damage site that is not at the edge of the capacitor and without obvious manifestations of Fabrication process anomalies such as bulging, void, unetched material or shifts in the planarity of the die layers. To further understand the defect site, Scanning Transmission Electron Microscopy (STEM) coupled with Energy-Dispersive X-ray Spectroscopy (EDS) were utilized to obtain high magnification imaging and elemental area mapping. Third, misled conclusion to be an EIPD site manifested by burnt and reflowed metallization. The EIPD site was only a secondary effect of a capacitor dielectric breakdown. This has been uncovered after understanding the circuit connectivity, inspections of the capacitors connected to the EIPD site, fault isolation and further physical failure analysis were performed. As results of the Failure Analysis (FA), Customer and Analog Devices Incorporated (ADI) manufacturing hold lots were accurately dispositioned and related corrective actions were precisely identified and implemented.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 62-66, November 12–16, 2023,
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Device shrinkage and mitigation of off-state power consumption are crucial factors in dynamic random access memory (DRAM) product development. Given the market demand for high-quality devices, the reduction and fluctuation of DRAM cell retention time, caused by interface traps, required a suitable solution for improved product quality. In this study, we propose a device structure for the reduction of GIDL current by implementing a second gate oxide in the overlapping region of the gate and the drain, and to calculate an increment in the margin for other processes from the retention time improvements, the virtual a capacitance of the bit line/a capacitance of the storage cap(Cb/Cs) evaluation was performed. This study is expected to provide a solution to the trap-induced retention- time deterioration and assist in the development of next-generation DRAM.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 85-91, November 12–16, 2023,
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Failure localization is one of the vital processes in the field of failure analysis. However, as newer fabrication processes emerge and demand for smaller transistors keeps on increasing, the complexity of failure analysis fault isolation involving micro-probing also increases along with the challenges on fault isolation equipment such as limited magnification and susceptibility to vibrations. In this paper, the capability of Focused Ion Beam (FIB) to perform circuit edit was utilized along with Avalon CAD navigation to pinpoint the location of the defects without the need of micro-probing while doing fault isolation. Results showed that through this technique, physical defect locations were successfully identified in three different case studies.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 101-104, November 12–16, 2023,
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The challenges keep rising for fault isolation and failure analysis (FIFA) for the advanced semiconductor devices fabricated via integrated processes. Perceiving that defects randomly occurred during IC manufacturing contribute primarily to the device failures in comparison to those caused by harsh service environmental, we focus our efforts on fixing the defect issues in the processes, expecting a significant portion of the device failures may be prevented. A case study here demonstrates the procedure for fixing an inline defect issue via improving tool maintenance for the chemical-mechanical polishing (CMP) process. Through a correlative physical and chemical analysis down to atomic scale, a 10 nm diamond particle and a 10 nm metallic debris damaging one of the metal interconnect layers were defined. The analysis led to pinpointing the issue to a metal CMP process. By examining the process operation and the tool configuration, we located the diamond-missing sites on a pad-conditioning disk made with embedded diamond grits in a metal matrix. Preventive countermeasure were implemented to avoid the same defect recurring via resetting the disk life and maintenance.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 131-135, November 12–16, 2023,
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Counterfeit integrated circuits (ICs) continue to persist in the supply chain causing early failure in electronics that unknowingly incorporate them. With counterfeiters becoming more adept at replicating ICs, the need for systems and processes to identify counterfeit ICs has been growing in recent years. In this paper, we benchmark the resonant cavity system (ResCav) by evaluating its ability to distinguish ICs with minor circuit variations. A baseline IC group along with 5 variant groups with changes made solely to their die were examined in this paper. Using a supervised machine learning algorithm, the system was able to distinguish every group of ICs amongst each other with an average weighted precision above 90% in every comparison scenario. The system’s ability to distinguish these subtle changes means that it would be suitable when used as a system for counterfeit detection, where the detection of minor deviations is pertinent. This could ultimately lead to the creation of a rapid, precise, and non-destructive system that can screen ICs for conformance.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 201-204, November 12–16, 2023,
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As technology nodes continue to shrink, Scanning Electron Microscopy (SEM) inspection and electrical characterization of transistors has increased in difficultly. This is particularly true with early back end-of-line (BEOL) features like metal and via layers which are traditionally imaged at 3-5 keV. At these layers, this energy is capable of beam contamination, introducing electrical complications particularly with transistor probing. This electrical data is necessary to characterize subtle defects at front end-of-line (FEOL). Thus, the implementation of beam deceleration for the inspection of these layers provides a useful combination of low landing energy and higher image quality. This technique proves to aid in preserving the ability to electrically characterize any defect at the subsequent layers beneath. This increases the quality of the Physical Failure Analysis (pFA) workflow when implemented at early BEOL layers by providing higher quality images as well as preserving the electrical properties of the transistors for subtle FEOL defect characterization.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 243-245, November 12–16, 2023,
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The development of modern power semiconductors requires the reduction of the resistance in the on-state of the device. One way to accomplish this is to reduce the bulk silicon thickness. To reach low final Si thicknesses, the grinding processes have to be adapted and optimized and new process-flows, such as dicing before grinding (DBG), must be employed.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 246-248, November 12–16, 2023,
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As the semiconductor process node enters into advanced process era, it is more challenging to extract electrical behavior of devices and circuits by nanoprobing systems. Not only probing is getting difficult at smaller contact or via, but also the deprocess tricks would have large influence on probing conditions, which could cause incorrect electrical performance and hard to explain the reasons. This research develops the technique of sample preparation to extract correct transfer curve of inverter cell in FinFET process.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 285-290, November 12–16, 2023,
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For decades, device scaling has been the primary driver of the performance boost in integrated circuit (IC) devices. However, this trend has slowed down in recent years due to physical limitations and technical challenges. To continue meeting the ever-increasing demand for high-performance computing, other innovations such as advanced transistor designs and packaging schemes have emerged. Advanced transistors, such as FinFETs and Gate-all-around FET (GAAFETs), have been developed to overcome the limitations of traditional planar transistors, offering higher performance and energy efficiency. Meanwhile, advanced packaging schemes, such as system-in-package (SiP), 2.5D, and 3D packaging, offer higher integration densities, improved thermal management, and faster data transmission. These innovations are crucial in driving the development of high-performance computing, and they will play an essential role in meeting the growing demand for faster and more efficient computing.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 300-304, November 12–16, 2023,
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Circuit edit (CE) workflows are well established for FIB energies of 30kV and above. The small spot size associated with such energies provides good milling acuity and imaging resolution needed for advanced CE applications. However, with the introduction of FinFET transistors and decreasing technology nodes, the dramatic reduction in STI to gate distance reduction poses some challenges to circuit editing at these high energies. These include transistor performance degradation due to Ga+ implantation as well as significant lateral scattering beyond the Node Access Hole (NAH) as defined by the pattern. In addition, the relatively fast milling speeds may not give enough control to the user to endpoint at the appropriate layer. In this paper, a group of FinFET transistors on a special test chip was edited with the Ga beam at different energies. Transistor performances were then characterized to evaluate any degradation. The resulting characterization revealed how the transistor performance was affected by the injected ion beams and provided a guideline for the low-kV circuit edit workflow. A novel low-kV FIB workflow was proposed to minimize the transistor damage and maintain the IC functionality after the CE process. The workflow was applied to a challenging CE problem on a 5nm FinFET device. This task included step by step backside delayering at 5kV, preparing the sample for the final circuit edit operation at Metal-1. Working at low landing energies (e.g. 5kV) lowers subsurface damage and reduces etching speed, but with trade offs including lower image resolution, milling acuity, sputtering yield and signal to noise ratio (SNR). However, the consequences of these effects can be mitigated by use of appropriate chemistries with closed loop delivery control and extremely low beam currents (≤1pA), in concert with double aperture beam shaping to minimize beam tails. On the 5nm FinFET device, we demonstrate good delayering control by optimization of beam currents, and gas delivery on the Centrios HX circuit edit system from Thermo Scientific.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 305-308, November 12–16, 2023,
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Miniaturization of today’s semiconductor devices and increased complexity of transistor architecture have resulted in gradually shrinking defect sizes. A direct consequence to this is the diminished chance of catching defects in the Transmission Electron Microscope (TEM) on the initial lamella, prompting the need to convert the TEM lamellas to analyze them from a different angle. In this work, a reliable step-by-step procedure to perform in-situ TEM lamella conversion is detailed. The applicability of the method is successfully validated on defective sub-20nm FinFET samples. Two different initial lamella types –planar and cross-sectional – are featured in the case studies to demonstrate the method’s versatility.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 352-359, November 12–16, 2023,
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Localizing security-relevant hard blocks on modern System-on-Chips (SoCs) for physical attacks, such as sidechannel analysis and fault attacks, has become increasingly time-consuming due to ever-increasing chip-area and - complexity. While this development increases the effort and reverse engineering cost, it is not sufficient to withstand resolute attackers. This paper explores the application of camera-based lock-in thermography (LIT), a nondestructive testing method, for identifying and localizing security hard blocks on integrated circuits. We use a synchronous signal to periodically activate security-related functions in the firmware, which causes periodic temperature changes in the activated die areas that we detect and localize via an infra-red camera. Using this method, we demonstrate the precise detection and localization of security-related hard blocks at the die level on a modern SoC.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 384-386, November 12–16, 2023,
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The operation of modern semiconductor components often relies on nanoscale electronic features emerging from complicated device architectures with finely tuned composition. While the physical structure of these devices may be straightforward to image, the resulting electronic characteristics are invisible to most high-resolution imaging techniques. Here we present electron beam-induced (EBIC) imaging in the scanning transmission electron microscope (STEM) as a high-resolution imaging technique with electronic-based contrast for characterizing complex semiconductor devices. Here, as an example case, we discuss the preparation and imaging of a STEM EBIC-compatible cross section extracted from a commercial AlGaAs high electron-mobility transistor (HEMT). The device exhibits low surface leakage, as measured via electrical testing and STEM EBIC conductivity contrast. The EBIC signal in the active layer of the device is mostly confined to the InGaAs channel, indicating that the electronic structure is largely preserved following sample preparation.
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