Abstract Correlation across applications and imaging platforms is essential and brings increased insurance for fault isolation in advance of destructive imaging. This paper demonstrates an approach for a detailed advanced packaging defect isolation and analysis workflow. To determine the effectiveness of the proposed workflow, a 28nm flip-chip was used as a test vehicle. By using this workflow, the yield in determining the fault location has increased from 60% to over 85%. To further improve the result, a surface charging mitigation scheme was used and the resulting measured correlative offset between the two systems was found to be less than 10um. This creates novel opportunities in reducing the size of the cross-section and increasing the overall throughput to find the defect, with high confidence. This workflow creates unique abilities in fault localization and analysis as it can detect both opens and shorts between the different techniques that are employed.

Abstract Fault localization using both dynamic laser stimulation and emission microscopy was used to localize the failing transistors within the failing scan chain latch on multiple samples. Nanoprobing was then performed and the source to drain leakage in N-type FinFETs was identified. After extensive detailed characterization, it was concluded that the N-type dopant signal was likely due to projections from the source/drain regions included in the TEM lamella. Datamining identified the scan chain fail to be occurring uniquely for a specific family of tools used during source/drain implant diffusion activation. This paper discusses the processes involved in yield delta datamining of FinFET and its advantages over failure characterization, fault localization, nanoprobing, and physical failure analysis.

Abstract The SuperCam instrument was selected by NASA in July 2014 and has been implemented on the Mars 2020 Perseverance rover. This instrumental suite gathers four different remote-sensing techniques including a very compact Infrared Spectrometer (IRS). For several reasons of costs and planning and after a risk mitigation phase, the use of full commercial-off-the-shelf photodiodes from TELEDYNE JUDSON J19 Series as detector for the IRS was decided. This paper describes the procurement, evaluation, and qualification philosophy of these photodiodes, providing information on the subsystems of the SuperCam instrument and the description of these photodiodes. Critical and fragile parts of the photodiode as the thermo electric cooler, have been particularly studied. In conclusion, the component was space qualified using the original use of the particle impact noise detection test applied for a mechanical screening purpose, with correlation between performance and fine leak, screening and the lot acceptance test processes.

Abstract The paper demonstrates accurate fault isolation information of metal-insulator-metal (MiM) capacitor failures by lock-in thermograph (LIT). In this study, a phase image spot location at a lock-in frequency larger than 5 Hz gives more accurate defect localization than an LIT amplitude image or OBIRCH to determine the next FA steps.

Abstract Failure analysis plays a very important role in semiconductor industry. Photon Emission Microscopy (PEM) has been extensively used in localization of fails in microelectronic devices. However, PEM emission site is not necessarily at the location of the defect. Thus, it has limitation for the success rate of the follow-up physical failure analysis focusing on the emission site. As semiconductor technology advanced in the 3D FinFET realm and feature size further shrank down, the invisible defects during SEM inspection are tremendously increased. It leads to the success rate further decreasing. To maintain good success rate of failure analysis for advanced 3D FinFET technology, electrical probing is necessary to be incorporated into the failure analysis flow. In this paper, first, the statistic results of PEM emission sites versus real defect locations from 102 modules of microprocessors manufactured by 14nm 3D FinFET technology was present. Then, we will present how to wisely design electrical probing plan after PEM analysis. The electrical probing plans are tailored to different scan chain and ATPG failures of microprocessors for improving failure analysis success rate without increasing too much turn-around time. Finally, two case studies have been described to demonstrate how the electrical probing results guide the follow-up physical failure analysis to find the defect.

Abstract In the failure analysis (FA) of modern semiconductor logic device manufactured in foundry fab, efficient identification of wafer edge’s defect was studied by using volume diagnosis analysis and plasma-focused ion beam (FIB) planar deprocessing. As the chip from wafer edge has multiple defective locations, there is the limitation of the conventional FA work to identify them. Here, we used volume diagnosis analysis to identify the multiple defective locations within chip and plasma-FIB planar deprocessing to delayer those locations and find out defects. The actual FA work verified that new workflow successfully identified the different defects from different layers from the chip of wafer edge and efficiently accelerated the quantity of FA results, importantly leading to more representative status of inline defect.

Abstract We present a new method for backside integrated circuit (IC) magnetic field imaging using Quantum Diamond Microscope (QDM) nitrogen vacancy magnetometry. We demonstrate the ability to simultaneously image the functional activity of an IC thinned to 12 µm remaining silicon thickness over a wide fieldof- view (3.7 x 3.7 mm 2 ). This 2D magnetic field mapping enables the localization of functional hot-spots on the die and affords the potential to correlate spatially delocalized transient activity during IC operation that is not possible with scanning magnetic point probes. We use Finite Element Analysis (FEA) modeling to determine the impact and magnitude of measurement artifacts that result from the specific chip package type. These computational results enable optimization of the measurements used to take empirical data yielding magnetic field images that are free of package-specific artifacts. We use machine learning to scalably classify the activity of the chip using the QDM images and demonstrate this method for a large data set containing images that are not possible to visually classify.

Abstract Getting accurate fault isolation during failure analysis is mandatory for success of Physical Failure Analysis (PFA) in critical applications. Unfortunately, achieving such accuracy is becoming more and more difficult with today’s diagnosis tools and actual process node such as BCD9 and FinFET 7 nm, compromising the success of subsequent PFA done on defective SoCs. Electrical simulation is used to reproduce emission microscopy, in our previous work and, in this paper, we demonstrate the possibility of using fault simulation tools with the results of electrical test and fault isolation techniques to provide diagnosis with accurate candidates for physical analysis. The experimental results of the presented flow, from several cases of application, show the validity of this approach.

Abstract Working on wafer-level has been the only way of performing electrical failure analysis (EFA) without the need for die-packaging. The introduction of Si-interposer based 2.5D packaging, with high bandwidth memory (HBM) stacks surrounding our GPU chip, drastically increasing packaging turn around times from approximately 3 days to 3-4 weeks. Having to wait more than 3 weeks for EFA and debug work of 1st Silicon chips is a significant risk for chip bring-up. To address these challenges, this paper presents different ways of reusing the existing wafer-level EFA tool for single die EFA, and introduces a concept for a novel and dedicated single die tool. Additionally, singulated die fixturing and support windows are designed to enable the usage of a 2.45 Numerical Aperture Solid Immersion Lens, and first results from a near reticle limited 16 nm Fin-FET GPU product are also presented.

Abstract Short wavelength probing (SWP) uses wavelengths of light shorter than 1100 nm or energies higher than silicon bandgap for laser probing applications. While SWP allows a significant improvement to spatial resolution, there are aberrations to the collected laser probing waveforms which result in difficulties in signal interpretations. In this work, we assess the signals collected through SWP (785 nm) and introduce a photodiode model to explain the observations. We also present a successful case study using 785 nm for failure analysis in sub-20 nm FinFET technology.

Abstract Focused Ion Beam (FIB) chip circuit editing is a well-established highly specialized laboratory technique for making direct changes to the functionality of integrated circuits. A precisely tuned and placed ion beam in conjunction with process gases selectively uncovers internal circuitry, create functional changes in devices or the copper wiring pattern, and reseals the chip surface. When executed within reasonable limits, the revised circuit logic functions essentially the same as if the changes were instead made to the photomasks used to fabricate the chip. The results of the intended revision, however, can be obtained weeks or months earlier than by a full fabrication run. Evaluating proposed changes through FIB modification rather than proceeding immediately to mask changes has become an integral part of the process for bringing advanced designs to market at many companies. The end product of the FIB process is the very essence of handcrafted prototyping. The efficacy of the FIB technique faces new challenges with every generation of fabrication process node advancement. Ever shrinking geometries and new material sets have always been a given as transistor size decreases and overall packing density increases. The biggest fundamental change in recent years was the introduction of the FinFET as a replacement for the venerable planar transistor. Point to point wiring change methodology has generally followed process scaling, but transistor deletions or modifications with the change to Fins require a somewhat different approach and much more careful control due to the drastic change in height and shape. We also had to take into consideration the importance of the 4 th terminal, the body-tie, that is often lost in backside editing. Some designs and FET technology can function acceptably well when individual devices are no longer connected to the bulk substrate or well, while others can suffer from profound shifts in performance. All this presents a challenge given that the primary beam technology improvements of the fully configured chip edit FIB has only evolved incrementally during the same time period. The gallium column system appears to be reaching its maximum potential. Further, as gallium is a p-type metal dopant, there are limitations to its use in close proximity to certain active semiconductor devices. Amorphous material formation and other damage mechanisms that extend beyond what can be seen visually when endpointing must also be taken into account [1]. Device switching performance and even transmission line characteristics of nearby wiring levels can be impacted by material structural changes from implantation cascades. Last year our lab participated in a design validation exercise in which we were asked to modify the drive of a multi-finger FinFET device structure to reduce its switching speed impact on a circuit. The original sized device pulled the next node in the chain too fast, resulting in a timing upset. Deleting whole structures and bridging over/around them is commonly done, but modifications to the physical size of an FET device is a rare request and generally not attempted. It requires a level of precision in beam control and post-edit treatment that can be difficult to execute cleanly. Once again during a complex edit task we considered the use of an alternate ion beam species such as neon, or reducing the beam energy (low kV) on the gallium tool. Unfortunately, we don’t yet have easy access to a versatile viable replacement column technology grafted to a fully configured edit station. And while there should be significantly reduced implant damage and transistor functional change when a gallium column FIB is operated at lower accelerating potential [2], the further loss of visual acuity due to the reduced secondary emission, especially when combined with ultra-low beam currents, made fast and accurate navigation near impossible. We instead chose the somewhat unconventional approach of using an ultra-low voltage electron beam to do much of the navigation and surface marking prior to making the final edits with the gallium ion beam in a dual-beam FIB tool. Once we had resolved how to accurately navigate to the transistors in question and expose half of the structure without disturbing the body-tie, we were able to execute the required cut to trim away 50% of the structure and reduce the effective drive. Several of the FIB modified units functioned per the design parameters of a smaller sized device, giving confidence to proceed with the revised mask set. To our surprise, the gallium beam performed commendably well in this most difficult task. While we still believe that an inert beam of similar characteristics would be preferable, this work indicates that gallium columns are still viable at the 14 nm FinFET node for even the most rigorous of editing requirements. It also showed that careful application of e-beam imaging on the exposed underside of FinFET devices could be performed without degrading or destroying them.

Abstract An advanced technique for site-specific Atom Probe Tomography (APT) is presented. An APT sample is prepared from a targeted semiconductor device (commercially available product based on 14nm finFET technology). Using orthogonal views of the sample in STEM while FIB milling, a viable APT sample is created with the tip of the sample positioned over the lightly-doped drain (LDD) region of a pre-defined PFET. The resulting APT sample has optimal geometry and minimal amorphization damage.

Abstract In the hardware assurance community, Reverse Engineering (RE) is considered a key tool and asset in ensuring the security and reliability of Integrated Circuits (IC). However, with the introduction of advanced node technologies, the application of RE to ICs is turning into a daunting task. This is amplified by the challenges introduced by the imaging modalities such as the Scanning Electron Microscope (SEM) used in acquiring images of ICs. One such challenge is the lack of understanding of the influence of noise in the imaging modality along with its detrimental effect on the quality of images and the overall time frame required for imaging the IC. In this paper, we characterize some aspects of the noise in the image along with its primary source. Furthermore, we use this understanding to propose a novel texture-based segmentation algorithm for SEM images called LASRE. The proposed approach is unsupervised, model-free, robust to the presence of noise and can be applied to all layers of the IC with consistent results. Finally, the results from a comparison study is reported, and the issues associated with the approach are discussed in detail. The approach consistently achieved over 86% accuracy in segmenting various layers in the IC.

Abstract Power consumption of conventional CMOS semiconductor architectures has grown to the point where novel structures need to be introduced to mitigate the power load within the chip. The introduction of the specialized artificial intelligence devices goes hand in hand with the inception of novel materials and processes into conventional semiconductor fabrication, which drives the need for expanding the host of failure analysis techniques and diagnostic capabilities. This paper describes a case study of elemental transmission electron microscopy tomography on an exploratory phase change memory test structure and comments upon some technique observations: advantages and disadvantages.

Abstract For advanced node semiconductor process development, manufacturing, fault isolation and product failure analysis, nanoprobing is an indispensable technology. As the process technology node scales, transistors and materials used are more susceptible to electron beam damage and changes. As scanning electron microscope (SEM) energy decreases to minimize electron beam damage, imaging resolution degrades. Process scaling has not only affected patterning dimensions and pitch scaling, but also materials utilized in advanced nodes. The material used at the contact level has changed from tungsten (W) to cobalt (Co), in combination with ultra-low K dielectrics. These new materials tend to make sample preparation and probing increasingly more challenging. At advanced nodes with sub-20nm contacts, probe landing accuracy and probe-contact stability are important to maintain good electrical contact throughout measurement time. In this paper, we discuss nanoprobing results from a 7nm SRAM obtained from a commercially available leading edge 7nm SOC.

Abstract A typical workflow for advanced package failure analysis usually focuses around two key sequential steps: defect localization and defect characterization. Defect localization can be achieved using a number of complementary techniques, but electro optical terahertz pulse reflectometry (EOTPR) has emerged as a powerful solution. This paper shows how the EOTPR approach can be extended to provide solutions for the growing complexity of advanced packages. First, it demonstrates how localization of defects can be performed in traces without an external connection, through the use of an innovative cross-sectional probing with EOTPR. Then, the paper shows that EOTPR simulation can be used to extract the interface resistance, granting an alternative way of quantitative defect characterization using EOTPR without the destructive physical analysis. These novel approaches showed the great potential of EOTPR in failure analysis and reliability analysis of advanced packaging.

Abstract As DRAM design rule (D/R) shrinks, the retention time due to leakage current becomes more important. Retention time failures that arise from gate induced drain leakage (GIDL) or junction leakage are exacerbated by changes in the electrostatic potential between adjacent lines or nodes. This study analyzes the effects of wordline (adjacent line) potential on retention time based on in sub-20nm DRAM technology. Electrical tests have confirmed that cells that fail from GIDL and junction leakage exhibit different behaviors according to the leakage characteristic and changes in adjacent wordline (especially in word-line across STI) potential. Simulations also confirm that these observations are due to the change in electric field. Based on these findings, a new perspective on the mechanism of retention failures is proposed.

Abstract As dimension shrinkage, uncommon phenomena have been occurring during write and read operation in DRAM. These phenomena are strongly related cell capacitance, and the sensitivity of leakage current increases. Leakage current, especially in cell capacitor or cell transistor, is a major cause of the imbalance between stored charge in write operation and served charge in the read operation. Generally, error induced by leakage current appears data-1 failure, but in our study data-0 failure is observed in the case of extreme low cell capacitance that failure level is ppb (parts per billion). Results show that this phenomenon is influenced by cell capacitance, gate/body voltage of cell transistor, and supplied voltage level of the bitline sense amplifier. Based on various results, the electron loss to form inversion electron channel of cell transistor is regarded as a major factor like Charge Feedthrough [5].

Abstract An experimental setup is presented, that allows in-situ Transition Electron Microscopy (TEM) investigation of void formation and growth within fully embedded interconnect structure, as a response to an external bias. A special TEM holder is employed to perform in-situ I-V measurements across the Via, simultaneously monitoring the morphological and chemical changes surrounding the void. This work presents in detail a Focused Ion Beam (FIB) based sample preparation method that allows the analysis of a Cu single Via structure found in the advanced microelectronic 14nm FinFET technology, as well as preliminary TEM observations.

Abstract In a previous study, the authors introduced a novel technique of using low-beam energy Gallium Focused Ion Beam to expose a large area of Shallow Trench Isolation (STI) over a Dynamic Ring Oscillator (DRO) incurring virtually no change of its operating frequency. In this paper, the authors further investigate the influence of extended dose delivery of 5 kV Ga+ after the initial exposure of the STI over a DRO on modern 7 nm process. The motivation of this study is to understand the dynamics between the Ga+ ion interaction at lower beam energies on live and functional devices and the failure mechanism of the device from such interaction. The frequency of the DROs after the initial STI exposure at 5 kV exhibits <1% increase. Additional dosage of lowkV exposure was performed over the exposed STI and its effects on the DRO frequency was monitored. Finally TEM analysis of the irradiated DROs will be analyzed to understand the failure mechanism of transistors.