Abstract The effect of copper (Cu) contamination inside the Si substrate from the wafer edge to the nearby devices has been investigated. After the Cu seed layer deposition, Cu contacted directly with Si at wafer edge where dielectric isolation layer was removed. Under the routine BEOL metallization and after the capping SiON/Si2O layers, SEM and AES analysis located a strip of islets of Cu contaminants. TEM analysis revealed that the seed Cu had interacted with Si substrate to form a stable ?-Cu3Si intermetallic compound that appeared to be planted into the Si substrate at the surface. SIMS analysis from the wafer backside, opposite to this strip of ?-Cu3Si islets at front, showed no Cu detection even after the majority of the backside Si was removed by grinding. Electrical nano-probing did not discern any parametric drift for the nanometer FinFET devices on chips near the edge surface of massive ?-Cu3Si islets in comparison with a reference chip from an uncontaminated wafer center. These results indicate that the formation of ?-Cu3Si, with a well-defined crystalline structure and a relatively stable stoichiometry, immobilizes Cu diffusion inside the Si substrate. In other word, the impact of Cu diffusion in Si has no effect on device performances as long as ?-Cu3Si is not directly formed in the FinFET channel or presents to short any structures within the chip.

Abstract Analog components are still an important aspect of our society's electronic portfolio. They play a role in the emerging and expanding 5G electronic industry, for instance. The NPN bipolar junction transistor (BJT) is the foundation of many analog circuits and has continually evolved to meet more demanding specifications [1], [2]. Certain embodiments of these NPNs pose difficulties in failure analysis. One such embodiment is a vertical NPN BJT with high aspect ratio dimensions. Specifically, the dimensions involved are nanometer thick NP & PN junctions that extend microns in length. These dimensions provide desired performance improvements but a subtle, nanometer scale defect present anywhere along this length can cause substantial electrical shifts detrimental to an analog circuit. Several simple and complex techniques using common failure analysis tools can isolate these defects as discussed in this paper.

Abstract The supply chain of the semiconductor industry is experiencing painful growth and advancement in chip development with the help of recently passed U.S legislation and funding to address a chip shortage. However, it is not without some drawbacks, one of which is the challenge of maintaining control over the manufacturing quality throughout the entire process. As a result of this, physical inspection for hardware security is a necessity to assure the semiconductor devices. In this paper, various physical inspection methods are reviewed and scanning acoustic microscopy (SAM) is proved to be the ideal physical inspection method to minimize the possibility of counterfeits which might be the feasible solution in detecting counterfeits on a large scale.

Abstract High performance IC's have driven the semiconductor industry towards the sub-nanometer technology nodes for several years. At 16nm and beyond, the spatial resolution and sensitivity of some diagnostic equipment used for failure analysis have reached certain limitations. The accuracy of isolating a faulty signal in a tightly packed group of transistors in a die becomes more challenging. However, with the improvement of SIL (Solid Immersion Lens) based lens technology with higher N.A. (Numeric Aperture), combined with precision die thinning process, allowed some very promising results. This paper demonstrates successful diagnostic techniques utilizing the SIL lens and a variety of die thinning preparation techniques on 7nm and 16nm process nodes in both monolithic and 2.5D SSIT (Stacked Silicon Interconnect Technology) packages.

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

Abstract The increasing trend for industry adoption of three-dimensional (3D) microelectronics packaging necessitates the development of new and innovative approaches to failure analysis. To that end, our team is developing a tool called the quantum diamond microscope (QDM) that leverages an ensemble of nitrogenvacancy (NV) centers in diamond for simultaneous wide fieldof- view, high spatial resolution, vector magnetic field imaging of microelectronics under ambient conditions [1,2]. Here, we present QDM measurements of two-dimensional (2D) current distributions in an 8 nm process node flip chip integrated circuit (IC) and 3D current distributions in a custom, multi-layer printed circuit board (PCB). Magnetic field emanations from the C4 bumps in the flip chip dominate the QDM measurements, but these prove to be useful for image registration and can be subtracted to resolve adjacent current traces on the micron scale in the die. Vias, an important component in 3D ICs, display only Bx and By magnetic fields due to their vertical orientation, which are challenging to detect with magnetometers that traditionally only measure the Bz component of the magnetic field (orthogonal to the IC surface). Using the multi-layer PCB, we demonstrate that the QDM's ability to simultaneously measure Bx, By, and Bz magnetic field components in 3D structures is advantageous for resolving magnetic fields from vias as current passes between layers. The height difference between two conducting layers is determined by the magnetic field images and agrees with the PCB design specifications. In our initial steps to provide further z depth information for current sources in complex 3D circuits using the QDM, we demonstrate that, due to the linear properties of Maxwell's equations, magnetic field images of individual layers can be subtracted from the magnetic field image of the total structure. This allows for isolation of signal from individual layers in the device that can be used to map embedded current paths via solution of the 2D magnetic inverse. Such an approach suggests an iterative analysis protocol that utilizes neural networks trained with images containing various classes of current sources, standoff distances, and noise integrated with prior information of ICs to subtract current sources layer by layer and provide z depth information. This initial study demonstrates the usefulness of the QDM for failure analysis and points to technical advances of this technique to come.

Abstract The sub-50 nm Indium Arsenide Composite Channel (IACC) High Electron Mobility Transistors (HEMTs) are fabricated on 100 mm Indium Phosphide (InP) substrates. This technology offers the best performance for low-noise and high-frequency, space and military applications. Typical failure mechanisms are observed in III-V HEMT technologies, including gate sinking, impact ionization and electromigration. Experiments were conducted to understand failure mechanisms of the IACC HEMTs by life testing devices at accelerated temperatures and biases; their electrical characteristics were measured at each stress interval. In order to determine which devices and where any defects occurred after the accelerated life tests, an additional test was completed, a Low-Noise Amplifier (LNA) Circuit assessment. The Low-Noise Amplifier (LNA) Circuit assessment determines which HEMT device is the weakest amongst the LNA circuit. Since many of the known III-V semiconductor failure mechanisms physically degrade or damage HEMTs, cross-sections are important to prepare to detect these mechanisms. In this presentation, advanced microscopy techniques with sub-nanometer resolutions, will examine physical characteristics of the HEMT at the atomic scale. The microscopy techniques will include a Focused Ion Beam/Scanning Electron Microscope (FIB/SEM), Nanomill and a Transmission Electron Microscope (TEM) along with Energy Dispersive Spectroscopy (EDS).

Abstract The use of optical techniques for attacking integrated circuits (ICs) at the silicon level is increasingly being reported. Although these attacks can be complex to set and require skilled attacker that can access expensive equipment, they are nonetheless very powerful. Among the different applications described in literature, there has been a focus on extracting data directly from embedded SRAM. Such attacks can provide access to highly sensitive information such as encryption keys and bypass various security strategies. An attacker usually exploits one of the several interactions that exist between light and semiconductor to generate an image where content can be directly qualified by the data in memory (Logic State Image – LSI). Thermal laser stimulation (TLS) and laser probing (EOFM-Electro-Optical Frequency Mapping) have been reported in the literature recently but Photoelectric Laser Stimulation (PLS) did not get as much attention. Considering the potential advantages of PLS over other techniques (e.g. lower power requirements to generate current/voltage change, effect can be triggered at shorter wavelength which may lead to an improved spatial resolution), we investigate in this paper if logic state images can be generated with PLS on a variety of devices and do a comparative assessment with state-of-the-art technologies to assess potential benefits and limitations.

Abstract Semiconductor manufacturing has been outsourced to un-trusted regions due to globalization. The complex multistep fabrication of micro-scale integrated circuits (ICs) and the tedious assembly of macro-scale Printed Circuit Boards (PCBs) are vulnerable to malicious attacks from design to final delivery. PCBs provide the functional connections of Integrated Circuits (ICs), sensors, power supplies, etc. of many critical electronic systems for consumers, corporations, and governments. The feature sizes of PCB signal traces in 2D and vias in 3D are an order of magnitude larger than IC devices, and are thereby more vulnerable to non-destructive attacks such as X-ray or probing. Active and passive countermeasures have been successfully developed for IC devices, however PCBs devices are difficult to wholly secure from all attacks. Passive countermeasures for X-ray attacks using high-z materials to block and scatter X-rays are effective, but there is a lack of active and passive countermeasures for PCB. In this paper, a framework for passively obfuscating a PCB's critical connections between components, such as ICs, from non-destructive attacks is demonstrated. This framework can be further extended to incorporate active countermeasures in future work. A proof of concept for a PCB electronic design automation (EDA) tool which combines the small features of micro electro-mechanical systems (MEMS), simulation of X-ray, and 3D PCB Manufacturing to iteratively optimize PCB design to thwart reverse engineering and probing attacks. Index Terms—Additive Manufacturing, MEMS, Hardware Assurance, Physical Inspection, Non-Destructive Technology

Abstract In response to a continually rising demand for high performance and low-cost devices, and equally driven by competitivity, the microelectronics industry excels in meeting innovation challenges and further miniaturizing products. However, device shrinkage and the increasing complexity of device architecture require local quantitative studies. In this paper, we demonstrate with a case study on a nanocapacitor, the capability of transmission electron microscopy in electron holography mode to be a unique in-situ technique for mapping electric fields and charge distributions on a single device.

Abstract The physical limits of CMOS scaling, as predicted by Moore's Law, should have already been reached several years ago. However, the scaling of transistors is still ongoing due to continuous improvements in material quality enabling the fabrication of complex device structures with nm-size dimensions. More than ever, the structural properties and the eventual presence of crystalline defects in the various semiconductor materials (SiGe, III/V) play a critical role. Electron channeling contrast imaging (ECCI) is a powerful defect analysis technique developed in recent years. The technique allows for fast and non-destructive characterizations with the potential for extremely low detection limits. The analysis of lowly defective materials requires measurements over large areas to obtain statistically relevant data. Automated ECCI mapping routines enable the quantification of crystalline defect densities as low as ~1e5 cm-2, e.g., Si0.75Ge0.25 strain relaxed buffers (SRB) epitaxially grown on a Si substrate. Methods to reduce the total measurement time without compromising its sensitivity will be discussed. The measurement routine has also been optimized to detect extended crystalline defects in III/V layers, selectively grown on shallow trench isolation patterned Si wafers. Throughout these examples, this study demonstrates the great potential of ECCI as a versatile and industry-relevant technique for defect analysis.

Abstract Planar deprocessing is a vital failure analysis (FA) technique for semiconductor chip reverse engineering. The basic concept of planar deprocessing is to remove all the “unnecessary” materials of a chip to expose an area of interest (AOI) and maintain the chip planarity and surface evenness. Finger deprocessing is one of the common techniques applied to this concept. This technique is essential in physical FA, especially for advanced bulk fin field-effect transistor (FinFET) devices. The success of finger deprocessing technique depends on certain factors, one of which is the location of AOI region. Application of finger deprocessing becomes incredibly challenging for AOI close to chip edge due to the chip edge effect, i. e. the chip edge is deprocessed much faster than the chip center. Plasma focused ion beam (PFIB) planar deprocessing is the primary solution to solve this problem. However, the PFIB capability is a luxury tool for most analysis labs. To overcome this challenge, a novel chip recombination method is introduced. With this method, planar deprocess can be achieved by conventional finger deprocessing technique and more importantly can be applied in general analysis labs. This paper will discuss the newly developed method in a step-by-step guide basis and show two cases with AOI(s) in the chip edge region to demonstrate its capability.

Abstract This research summarizes failure analysis results about ionimplantation related issues in Si-based power devices, including diode, MOSFET and IGBT. To find out this kind of defects, sample preparation, fault isolation and SCM inspection are critical steps, which will be explained in detail in this paper.

Abstract With the increase in the complexity of semiconductor wafer fabrication processes, the timing in responding and discovering the failure mechanism to a product failure at the initial product development stage or at the end of production line becomes a crucial factor. Effectively utilization the fault localization technique such as Photon Emission Microscopy (PEM), Laser Signal Injection Microscopy (LSIM) and Thermal Hotspot Localization (THS) may be significantly shortened the cycle time in the fault localization process. This paper will illustrate the creative approaches for thermal hot spot identification using modulated THS technique coupled with modified external electrical connection.

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

Abstract MIM (Metal-Insulator-Metal) capacitor is a capacitor fabricated between metal layers and usually in an array form. Since it is usually buried within stack of back-end metal layers, neither front side nor backside FA fault isolation techniques can easily pinpoint the defect location of a failing MIM capacitor. A preliminary fault isolation (FI) often needs to be performed by biasing the desired failing state setup to highlight the difference(s) of FI site(s) between failing unit & reference. Then, a detailed study of the CAD (Computer Aided Design) schematic and die layout focusing on the difference(s) of FI site(s) will lead to a more in-depth analyses such as Focused Ion-Beam (FIB) circuit edit, micro-probing/nano-probing, Voltage Contrast (VC) and other available FA techniques to further identify the defective MIM capacitor. Once the defective MIM capacitor was identified, FIB cross-section or delayering can be performed to inspect the physical defect on the MIM capacitor. This paper presents the FA approach and challenges in successfully finding MIM capacitor failures.

Abstract The development of advanced logic processing technologies has hit a critical slowing period over the past 10 years. Long gone are the booming days of exponential growth seen in chip transistor density as described by Moore's Law back in 1965.[1] With modern logic manufacturers now capable of creating transistors in the 5-7 nm node range, having the ability to isolate, inspect, and probe individual metal and via layers is of utmost importance for defect inspection and design validation. In this realm of failure analysis, it is critical that design manufacturers possess the ability to isolate any given single layer of their logic samples. These isolated layers can be inspected for defects via SEM, provide validation of CAD designs, or tested with electrical probing for failure analysis. The work here-in describes a functional workflow that enables manufacturers to perform this kind of sample preparation in an automated fashion using the Thermo Scientific™ Helios™ G5 PFIB platform. This workflow can be utilized by both the Thermo Scientific Full Wafer and Small Dual Beam PFIB platforms to streamline sample analysis and failure testing in both the lab and fabrication environments.

Abstract The integrity of a P-type or N-type epitaxial layer, implanted wells, or dopants (i.e. P-epi, N-well, P-imp, N-imp, etc.) oftentimes can affect the performance of an integrated circuit (IC), especially in analog/mixed signal devices. At onsemi, we had encountered a poor P-N junction of a Zener diode that caused a Cross-Coupled-Switched-Cap voltage doubler to have a lower output voltage which eventually affected the performance of the IC. The integrity of any P-N junction can be electrically verified through curve tracing with in-SEM nano-probing and fault isolation (PEM, OBIRCH, etc.) techniques. However, physical defect revelation using junction stain, either top-down or in cross section, can be challenging due to the three-dimensional (3D) form of any P-N junction. With Electron Beam Induced Current (EBIC), we can easily identify an abnormal P-N junction through both topdown and cross section. This paper is to characterize EBIC analysis on IC cross sectional view in mapping the P-N junctions and provide the information of its doping profiles. In this paper, limitation of both chemical etching and EBIC will be discussed as well as introducing the use of ion mill after FIB cross section during cross sectional EBIC sample prep as a potential method for resolution enhancement. These findings add to the understanding in using this technique and further improvement to its application in failure analysis.

Abstract For a specific IDDQ failure only around SRAM cell boundary, we conducted a systematic investigation in the lab involving electrical, physical, and chemical analysis. Following electrical test locating the failure area according to PEM (photon emission microscopy) and physical defect analysis resulting in NDF (no defect found), we explored an alternative method to define the failure. In this paper, we demonstrated the success of using tunneling AFM (TUNA) in diagnosing such an IDDQ failure occurring in FinFET devices. AFM (TUNA) analysis was able to visualize clearly the dopant discrepancies in comparison between the IDDQ fail and pass references in FinFET transistors. The dopant abnormalities indicated the current IDDQ fail was caused by processes that impaired the dopant implantation.

Abstract Narrowing design and manufacturing process margins with technology scaling are one of the causes for a reduction in IC chip test margin. This situation is further aggravated by the extensive use of third-party design blocks in contemporary system-on-chips which complicates chip timing constraint. Since a thorough timing verification prior to silicon fabrication is usually not done due to aggressive product launch schedules and escalating design cost, occasionally, a post-silicon timing optimization process is required to eliminate false fails encountered on ATE. An iterative two-dimensional shmoo plots and pin margin analysis are custom optimization methods to accomplish this. However, these methods neglect the interdependencies between different IO timing edges such that a truly optimized condition cannot be attained. In this paper, we present a robust and automated solution based on a genetic algorithm approach. Elimination of shmoo holes and widening of test margins (up to 2x enhancements) are demonstrated on actual product test cases. Besides test margin optimization, this method also offers insights into the criticality of test pins to accelerate failure debug turnaround time.