In this paper, we demonstrate three approaches to enhance the topographical contrast of infrared images obtained from lockin thermography (LIT). Infrared imaging, particularly LIT, is one of the extensively used techniques for failure analysis (FA) in the semiconductor industry. However, low-contrast topography images are obtained at room temperature from conventional LIT due to poor emissivity contrast in the devices and the limitation on the performance of the infrared camera. The gray-scale topographical contrast is improved by 85% when the device under test is heated from room temperature to 75°C, using a printed circuit board heater. Furthermore, a heat-assisted LIT approach is proposed and demonstrated at the die level on an electrically leaky silicon interposer sample. The topographical contrast and the signal intensity of the hotspot obtained are enhanced when compared to the classical LIT, which is performed at room temperature. Further, the dual LIT approach is developed to reduce the thermal budget of the heat-assisted approach. The hotspot amplitude and improved topography image are obtained from two consecutive lock-in measurements. In addition, the topography image from this technique is obtained by averaging several hundred frames from the camera for a period of ten minutes, which results in an image that is less susceptible to input noise levels. To increase the throughput of the FA process, quadrature lock-in thermography, a dual-purpose measurement technique is shown. A high-contrast topography image and the hotspot location are obtained from the same lock-in thermogram by performing trigonometric conditioning. The throughput from this approach is the same as the classical LIT technique.

Infrared lock-in thermography systems are frequently utilized for non-destructive failure analysis of integrated circuits due to sensitivity of the thermal detector to small temperature changes from electrical activity. This thermal sensitivity can also be leveraged for design verification and debug of device thermal management via absolute temperature mapping. The application of temperature mapping to a device under test (DUT) that requires boards and sockets, such as in tester based applications, has traditionally been challenging, due to the requirement that the DUT not be moved and the difficulty of heating the DUT through the thermal mass of the boards and sockets to which the DUT is mounted. This paper describes a proposed alternative single-temperature in-situ calibration method to eliminate the need for a heated thermal chuck for absolute temperature mapping. Preliminary results are promising and show that the new alternative single-temperature in-situ method results in temperature measurements within 1 °C close to room temperature and within 2.5 °C at elevated temperatures up to approximately 75 °C, as compared to the 1 °C accuracy of the current standard two-temperature in-situ method. While this alternate method is not as accurate as the standard two-temperature in-situ calibration method, the fact that it can be performed at a single room temperature means that it enables absolute temperature mapping for use cases requiring boards or socketed DUTs, as is the case for tester applications. An example characterization of a DUT utilizing varying clock signal inputs shows the added flexibility and ease of setup that the alternative single-temperature workflow brings, creating new opportunities for use-cases such as boards and testers where the use of a heated thermal chuck is not viable.

Lock-in thermography (LIT) is a firmly established and powerful technique for IC defect localization. The standard approach is to detect and analyze the device temperature fluctuation between two bias conditions using an infrared thermal imaging camera and check for any anomalous heat response. For the most straightforward setup, these bias conditions would be achieved by the modulation of a supply voltage provided by the LIT system. This allows for synchronization to the internal camera frame rate. In addition to this method, the ability to provide an external trigger may be an option, as it is for the ELITE system by Thermo Fisher Scientific. This expands the LIT arena to failures that may only be observable by, for example, setting different register contents at a constant supply voltage. Though IC testers can be used to provide the stimulus and a trigger signal for these situations, often a simpler, more compact solution would be beneficial for the failure analyst. This paper presents such an alternative: the application of a low-cost, USB-based module which can emulate various communication protocols (for example, I 2 C, SPI) while providing a synchronized timing pulse to externally trigger the ELITE, thus facilitating dynamic LIT investigations. The efficacy of this solution is demonstrated by a case study in which dynamic LIT produced a single hot spot at the defect site that was undetected by the voltage modulation approach.

This article describes a method that combines Analog Signature Analysis (ASA) with IR based Direct Current Injection (IRDCI) for printed circuit board assembly failure analysis. The integration of ASA extends the diagnostic capability of IRDCI from shorted power rails to any measurement location that shows signature differences. It also facilitates the detection of electrical breakdown or degradation without having to remove suspected faulty components from the board.

The application of IR-Lock-In Thermography (IRLIT) has been extended from 2D and 3D package fault isolation to on-die level analysis. In addition, the technique has become more sensitive allowing for detection of much lower dissipated power. In this paper, several fault localization cases covering PCB assemblies down to die level analysis are discussed using IR-LIT and absolute temperature mapping. Where possible, the analysis is complemented with physical defect verification. The fault isolation cases include an ultra-low power dissipation (<150 nW) and several case studies with high ohmic connections. For the latter a new method based on phase mapping is discussed allowing for 2D localization of thermally invisible defects. The method will be demonstrated on a test vehicle where phase data extracted from a visible feature of the device under test is studied. After this, a case study at die level is presented in an attempt to distinguish the phase information from two stacked M2-M3 metallization layers of the Back-End Of the Line (BEOL). Finally, temperature mapping results of a 5 micron wide aluminum feature in silicon-oxide is presented that is pushing the optical resolution of the tool.

Lock-in thermography (LIT), known as a powerful nondestructive fault localization technique, can also be used for microscopic failure analysis of integrated circuits (ICs). The dynamic characteristic of LIT in terms of measurement, imaging and sensitivity, is a distinct advantage compared to other thermal fault localization methods as well as other fault isolation techniques like emission microscopy. In this study, LIT is utilized for failure localization of units exhibiting functional failure. Results showed that LIT was able to point defects with emissions in the mid-wave infra-red (MWIR) range that Photo Emission Microscopy (PEM) with near infrared (NIR) to short- wave infra-red (SWIR) detection wavelength sensitivity cannot to detect.

Thermal issues management is a daily design challenge for teams working with analog mixed-signal technologies such as “SmartMOS”, with the integration of analog circuitry, high power density devices and logic control. A case study based on an NXP new product introduction will illustrate the use of Thermography as a complementary technique to standard Design debug activities, leading to the demonstration of a thermal crosstalk phenomenon in the analyzed analog mixed signal device. Based on InfraRed Thermography principle and specific Trigger Delay and Thermal Mapping modes, a transient thermal event was fully characterized, in addition to more common techniques such as Design and Layout study, electrical characterization, simulation, Microprobing, and Thermal Laser Stimulation. The added value of the thermography, as well as the limitations of the technique, will be discussed in that paper.

Fault localization is a common failure analysis process that is used to detect the anomaly on a faulty device. The Infrared Lock-In Thermography (LIT) is one of the localization techniques which can be used on the packaged chips for identifying the heat source which is a result of active damage. This paper extends the idea that the LIT analysis for fault localization is not only limited to the devices within the silicon die but it also highlights thermal failure indications of other components on the PCB (like capacitors, FETs etc on a system level DC-DC μmodule). The case studies presented demonstrate the effectiveness of using LIT in the Failure analysis process of a system level DC-DC μmodule regulator.

In this paper, we present a technique for device temperature measurement using spontaneous near infrared (NIR) emission from an Integrated Circuit (IC). By leveraging modeling and data analysis, time-integrated emission measurements are used to estimate the temperature increase due to switching activity inside the channel of CMOS transistors. The non-invasive nature of the technique allows one to reliably monitor the temperature of any device on-chip without the need for circuit modifications or dedicated on-chip sensors and with a higher spatial resolution than thermal cameras. This method has important applications for modeling heat dissipation during early process development, localizing hot spots, calibrating on-chip sensors, etc. In this paper, temperature is estimated by fitting empirical emission data to an emission model that can be solved for device channel temperature.

Photoluminescence, defect-band emission, and Lock-in Infrared Thermography (LIT) generally enable the correlation of multi-crystalline silicon defect types. Long Wavelength Infrared (LWIR) thermal imaging has traditionally seen limited application in failure analysis. LWIR cameras are typically uncooled systems using a microbolometer Focal Plane Arrays (FPA) commonly used in industrial IR applications, although cooled LWIR cameras using Mercury Cadmium Tellurium (MCT) detectors exists as well. On the contrary, the majority of the MWIR cameras require cooling, using either liquid nitrogen or a Stirling cycle cooler. Cooling to approximately −196 °C (77 K), offers excellent thermal resolution, but it may restrict the span of applications to controlled environments. Recent developments in LWIR uncooled and unstabilized micro-bolometer technology combined with microscopic IR lens design advancements are presented as an alternative solution for viable low-level leakage (LLL) defect localization and circuit characterization. The 30 micron pitch amorphous silicon type detector used in these analyses, rather than vanadium oxide (VOx), has sensitivity less than 50mK at 25C. Case studies reported demonstrate LWIR enhanced package-level and die-level defect localization contrasted with other quantum and thermal detectors in localization systems.

In this paper, we discuss a set of techniques and analysis methodologies for the reverse engineering and functionality extraction of complex mixed-signal ICs with a special focus for security applications. Front and back side reflected light pattern images at different magnifications are used to identify circuit blocks. Time-integrated and time-resolved photon emission data is used to identify gate logic states, sequences of events, and specific functional activity. Backscattered electron and scanning transmission electron images mosaics are used to reverse engineer individual gates and observe local interconnects. Thermal imaging is used to aid in the functional block identification and analog gates analysis. Different advanced methodologies for tool automation, focusing, mapping, and image processing are also discussed in the context of our proposed electro-optical tester based technique.

A Flip Chip sample failed short between power and ground. The reference unit had 418Ω and the failed unit with the short had 16.4Ω. Multiple fault isolation techniques were used in an attempt to find the failure with thermal imaging and Magnetic Current Imaging being the only techniques capable of localizing the defect. To physically verify the defect location, the die was detached from the substrate and a die cracked was seen using a visible optical microscope.

This paper shows a specific approach based on infrared (IR) thermography to face the challenging aspects of thermal measurement, mapping, and failure analysis on AlGaN/GaN high electron-mobility transistors (HEMTs) and MMICs. In the first part of this paper, IR thermography is used for the temperature measurement. Results are compared with 3D thermal simulations (ANSYS) to validate the thermal model of an 8x125pm AIGaN/GaN HEMT on SiC substrate. Measurements at different baseplate temperature are also performed to highlight the non-linearity of the thermal properties of materials. Then, correlations between the junction temperature and the life time are also discussed. In the second part, IR thermography is used for hot spot detection. The interest of the system for defect localization on AIGaN/GaN HEMT technology is presented through two case studies: a high temperature operating life test and a temperature humidity bias test.

Lifted bond balls in Integrated Circuit (IC) have numerous failure mechanisms. A simple external curve can confirm the open, and with package decapsulation, lifted balls can be readily observed. However, the exact cause can be difficult to identify. Most often, a cross section through the balls was performed, but it is far from being able to reveal the reason for lifted bond balls. A comprehensive FA approach is needed. Performing failure analysis through the back side of the die using Scanning Acoustic Microscopy (C-SAM) and Infra Red (IR) inspection helps to observe the conditions of the bond pads. Pulling the die from the mold compound can provide a pristine view of the bond ball-bond pad interface. This allows the detection of contaminants, both organic and inorganic, which cross sections cannot provide.

The continuous miniaturization trends followed by a vast majority of electronic applications results in always denser PCBs (Printed Circuit Board) designs and PCBAs (Printed Circuit Board Assembly) with increasing solder joint densities. Current high-end designs feature high layer count sequential build-up PCBs with fine lines/spaces and numerous stacked filled microvias, as well as closely spaced BGA/QFN components with pitches down to 0.4mm. In recent years, several 3D packaging approaches have emerged to further increase system integration by enabling the stacking of several dies or packages. This has translated for example into the advent of highly integrated complex System in Package (SiP) modules, Package-on-Package (PoP) assemblies or chips embedded in PCBs [1]. From a failure analysis (FA) perspective, this deep technology evolution is setting extreme challenges for accurately locating a failure site, especially when destructive techniques are not desired. The few conventional non-destructive techniques like optical or x-ray inspection are now practically becoming useless for high density PCB designs. This paper reviews several advanced analysis techniques that could be used to overcome these limitations. It will be shown through several examples how three non-destructive methods usually dedicated to package analyses can be efficiently adapted to PCBs and PCBAs: • Scanning Acoustic Microscopy (SAM) • 3D X-ray Computed Tomography (CT) • Infrared Thermography A case study of a flex-rigid board FA is presented to show the efficiency of these three techniques over classical techniques. In this example, not only the defect localization has been possible, but also the defect characterization without using destructive analysis.

Counterfeit components have been defined as a growing concern in recent years as demand increases for reducing costs. In fact the Department of Commerce has identified a 141% increase in the last three years alone. A counterfeit is any item that is not as it is represented with the intention to deceive its buyer or user. The misrepresentation is often driven by the known presence of defects or other inadequacies in regards to performance. Whether it is used for a commercial, medical or military application, a counterfeit component could cause catastrophic failure at a critical moment. The market for long life electronics, based on commercial off the shelf (COTS) parts, such as those used in medical, military, commercial depot repair, or long term use applications (e.g. street and traffic lights, photovoltaic systems), seems to create a perfect scenario for counterfeiters. With these products, components wear out and need to be replaced long before the overall product fails. The availability of these devices can be derived in many ways. For example, a typical manufacturer may render a component obsolete by changing the design, changing the functionality, or simply discontinuing manufacture. Also, the parts that are available after a design has been discontinued are often distributed by brokers who have very little control over the source or supply. Recycling of devices has also emerged as a means of creating counterfeit devices that are presented as new. And finally, as demand and price increase, the likelihood of counterfeits also increases. This paper will address the four unique sources of counterfeit components and insight into how they occur. Detection methodologies, such as visual inspection, mechanical robustness, X-Ray, XRF, C-SAM, Infrared Thermography, electrical characterization, decapsulation, and marking evaluations, will be compared and contrasted, as well as multiple examples of counterfeit parts identified by DfR.

In this paper, investigations on absolute temperature measurements using IR-Thermography of CMOS integrated micro-hot-plates (μHP) are presented. The results of using two different approaches, emissivity correction and black paint coating, are presented and compared with respect to simulation and electrical testing results. In addition, FIB/SEM investigations were used for surface investigations and determination of possible influences to the thermal behaviour by black paint coating process.

This paper focuses on infrared (IR) thermography capabilities on III-V components for thermal measurements applications and failure analysis (FA). The first part discusses the thermal mapping on InGaAs/AlGaAs PHEMT structure and compares IR thermal measurement with the well-known techniques as Raman and SThM. The second part discusses IR thermography on challenging FA for hot spot detection on the most popular type of capacitor for III-V MMICs as the metal-insulator-metal capacitor. It shows how IR thermography can easily localize very small pinholes in SiN, where liquid crystal and OBIRCH techniques are not well adapted.

We report on the development of a novel thermography technique, integrated Raman – IR thermography, illustrated here on AlGaN/GaN electronic devices. As it is a generic technique future application to Si, GaAs and other devices is anticipated. While IR thermography can provide fast temperature overviews, its current use for many of today’s technologies is complicated by the fact that it does not provide the spatial resolution needed to probe sub-micron/micron size active device areas. Integrating IR with micro-Raman thermography, providing temperature information with ~0.5 µm spatial resolution, enables unique thermal analysis of semiconductor devices to a level not possible before. This opens new opportunities for device performance and reliability optimization, and failure analysis of modern semiconductor technology, in research, development, and quality control / manufacturing environments.

A hemispherical silicon solid immersion lens (SIL) was used to improve the spatial resolution of front-side thermal IR imaging in lock-in mode. The bottom of the SIL was coneshaped to reduce the footprint of the SIL to the size of the imaged region. Caused by the lock-in operation mode, the detection limit improves by 2-3 orders of magnitude, and scattered light does not limit the image contrast. By using this SIL in combination with an IR camera working in the 3-5 μm wavelength range, a spatial resolution of 1.4 μm was obtained for thermal IR imaging. An automatic SIL positioning facility was constructed to place the SIL exactly in the center of the imaged region and to easily remove it after the detailed investigation.