Board level semiconductor reliability testing (BLTT) is a crucial step in the product development life cycle of modern electronics. While the primary focus of semiconductor reliability historically has been to understand the robustness of the solder joint, there are other aspects of the semiconductor package which are also susceptible to failure after the product has been assembled. Despite its overwhelming importance, there is no one centralized resource outlining best practices for conducting BLRT across industries. Fortunately, industry standards do exist. Among them are outlines for conducting tests including temperature cycling, mechanical shock, humidity dwell among others. In this work we present a case study exploring some of the unique challenges and methods associated with conducting BLRT using mechanical shock testing. Namely, we discuss the practical challenges of conducting these tests in the presence of a constant noise source and performing die level failure analysis on components suffering from warpage while back side films (BSFs) are applied as a protective coating on the package.

Currently, wire bonding is still the dominant interconnection mode in microelectronic packaging, and epoxy molding compound (EMC) is the major encapsulant material. Normally EMC contains chlorine (Cl) and sulfur (S) ions. It is important to understand the control limit of Cl and S in the EMC to ensure good Au wire bond reliability. This paper discussed the influences of Cl and S on the Au wire bond. Different contents of Cl and S were purposely added into the EMC. Accelerated reliability tests were performed to understand the effects of Cl, S and their contents on the Au wire bond reliability. Failure analysis has been conducted to study the failure mechanism. It is found that Cl reacted with IMCs under humid environment. Cl also caused wire bond failure in HTS test without moisture. On the other hand, the results showed that S was not a corrosive ion. It was also not a catalyst to the Au bond corrosion. Whilst, high content of S remain on the bond pad hindered the IMCs formation and caused earlier failure of the wire bond.

Traditionally, reliability defects are addressed by end-of-line electrical measurements and extensive and dedicated testing during packaging. These tests cover almost every known defect condition and ensure product reliability with high confidence, but they occur in the final stage of manufacturing and are quite time intensive. This paper shows that inline reliability metrology based on Raman spectroscopy is an effective approach for early fault detection and can be used to monitor unintended epi growth, strain, lattice defects, stacking faults, dislocations, and post-etch residues. It can also reveal process anomalies and potential material problems. The paper examines the relationship between process parameters and reliability and reviews the enablers of preventive, early-detection inline metrology in the fab.

Redistribution layer (RDL) bonding pad over active circuitry is utilized to re-route the original bond pad to other location for wire bonding using RDL. The damages in the active circuitry beneath the RDL bond pad induced by stress from wire bonding and package must be evaluated for reliability in the product development. The experimental approach and test structures are proposed in this paper. Functional fail was detected in electrical test after reliability tests on packaged IC. The dielectric cracking initiated by wire bonding that corresponds to the functional fail is identified by physical failure analysis and Transmission-Electron-Microscopy (TEM) at a specific location beneath the RDL bond pad. Finite element simulations are used to analyze the wire bonding stress distribution and circuit-under-pad design effect. The predicted maximum stress for the dielectric cracking matches to the location observed in the physical failure analysis. Based on the experiment and the simulation data, design rules for the circuit routing beneath the RDL bond pad have been successfully developed that all product reliability tests pass later with extend bonding power. The results lead to significant improvements in the robustness of circuit routing structure beneath the RDL bond pad for dielectric cracking without modifications of the existing processes for the product.

Reliability tests, such as Time-Dependent Dielectric Breakdown (TDDB), High-Temperature Operating Life (HTOL), Hot Carrier Injection (HCI), etc., is required for the lifetime prediction of an integrated circuit (IC) product. Those reliability tests are more stringent and complex especially for automotive Complementary Metal–Oxide–Semiconductor (CMOS) devices, this because it involves human lives and safety. In foundries failure analysis (FA), Transmission Electron Microscopy (TEM) analysis often required in order to provide insights into the defect mechanisms and the root cause of the reliability tests. In this paper, application of high resolution Nano-probing Electron Beam Absorbance Current (EBAC), Nano-probing active passive voltage contrast (APVC), and TEM with Energy Dispersive X-Ray Spectroscopy (EDX) to identify the failing root cause of Inter- Poly Oxide (IPO) TDDB failure on an automotive grade Non- Volatile Memory (NVM) device was investigated. We have successfully demonstrated that TEM analysis after Nanoprobing EBAC/APVC fault isolation is an effective technique to reveal the failure root cause of IPO breakdown after reliability stresses.

NCF (Non Conductivity Film) is a material used for under-fill purpose in the TSV (Through Silicon Via) process, and is a key material for ensuring TSV 3D Package (PKG) reliability. Among the types of defects generated by the NCF, the most typical type is delamination. Particularly in NCF delamination frequently occurs during reliability test, we analyzed chemical state change of NCF according to reliability test step/condition by utilizing FTIR and TMA. Through these studies, we clarify the cause of Delamination.

The degraded performance of a power MOSFET affects customer system reliability and consumer perceptions of quality. Building a reliable product and associated application specific lifetime models to predict the suitability of a power device for a given solution can enable competitive advantages, increased quality, enhanced performance and result in market share gains. This paper describes the methodology employed to configure an application specific reliability test, the failure rates and modes observed, the package modelling, and design improvements implemented. The validation of such relative to its original form and competitor products is discussed where we demonstrate a doubling in performance and an approximate 50% increase in current handling capability. This type of analysis and application specific approach to innovation enables one to focus design improvements in areas most relevant to customer concerns while at the same time adding credibility to specified product limits.

This paper presents a quick, reliable, and fully quantitative method of measuring the intermetallic coverage of copper to aluminium bonding at time zero and post reliability stressing. This method is currently used in select manufacturing quality control processes, as well as during product release procedures. By applying this measurement method after various life-tests, it has been possible to collect information on degradation in the copper aluminium system which is currently being used to make a model of the corrosion mechanism in the copper aluminium system.

In this paper, we propose a new methodology and test system to enable the early detection and precise localization of Time-Dependent-Dielectric-Breakdown (TDDB) occurrence in Back-End-of-Line (BEOL) interconnection. The methodology is implemented as a novel Integrated Reliability Test System (IRTS). In particular, through our methodology and test system, we can easily synchronize electrical measurements and emission microscopy images to gather more accurate information and thereby gain insight into the nature of the defects and their relationship to chip manufacturing steps and materials, so that we can ultimately better engineer these steps for higher reliable systems. The details of our IRTS will be presented along with a case study and preliminary analysis results.

An advanced method for LF (Lead Free) bump sample preparation to improve the surface of sample that can enhance the image of IMC (Inter Metallic Compound), solder grain boundary and micro-crack after TC (thermal cycle) reliability test is proposed. By this advanced method application, LF bump micro-crack location and propagation path can be observed easily for the reliability test fracture failure mechanism study and LF bump crack improvement further.

Thick film resistors are widely used in consumer and industrial products such as timers, motor controls and a broad range of high performance electronic equipment. This article provides information on failures due to copper dendrite growth, silver migration, sulfur atmosphere corrosion, variation of temperature, and crack due to molding compound mechanisms. It presents case studies in which a physical analysis plan was developed and executed to investigate these sites of interest on as-manufactured and failed thick film power resistors. The analysis techniques included X-ray inspection, cross-sectioning, decapsulation, and optical and environmental scanning electron microscopy analysis. A table illustrates different failure modes and mechanisms for thick film resistors, and also potential application and manufacturing factors that cause failure mechanisms, which then describe the failure modes. The article is concluded that by preventing the failure of thick film resistors, printed circuit boards can be kept in service for their full lifetime.

The reliability of a pure CMOS One-time Programmable (PCOP) Memory was investigated. The memory is programmed with and anti-fuse formed by the breakdown of the thin gate oxide. The results of reliability stress tests show that the PCOP memory is stable and reliable for normal using environmental conditions.

During moisture-and-bias reliability stress tests of THBT (temperature and humidity biased test) and HAST (highly accelerated stress test) extensive electrochemical oxidation of a TiN ARC layer is seen to occur. This oxidation proceeds at the nominal temperatures and humidity levels associated with such THBT and HAST tests; excessive heating due to EOS (electrical overstress) or other anomalous electrical conditions was not involved. The oxidation rate increases with applied voltage. Metal line width also affects the spread of oxidation. Oxidation requires the presence of adequate humidity to act as an electrolyte, and therefore is seen to propagate wherever moisture penetration can occur in the passivation dielectrics. The presence of a silicone gel die coating is found to render the die more susceptible to TiN oxidation. Electrical failures – typically open circuits or increased resistance due to corrosion – are found to occur as a consequence of this oxidation and its effect on the surrounding structures. This mechanism is a concern for integrated circuits with TiN in the upper metal layers, operating at voltages >5V in humid conditions. Two approaches at reducing this electrochemical reaction are offered.

The paper focuses on the pad contamination defect removal technique. The defect is detected at the outgoing inspection step. The failure analysis results showed that the defect is Fluorine type contamination. The failure analysis indicated many source contributors mainly from Fluorine based processes. The focus is in the present work is in the rework method for the removal of this defect. The combination of wet and dry etch processing in the rework routine is utilized for the removal of the defect and preventive action plans for in-line were introduced and implemented to avoid this event in the future. The reliability of the wafer is verified using various tests including full map electrical, electrical sort, gate oxide breakdown (GOI) and wafer reliability level, passivation quick kill to ensure the integrity of the wafer after undergoing the rework routine. The wafer is monitored closely over a period of time to ensure it has no mushroom defect.

Packages with the Modified Daisy-chain (MDC) die have been used increasingly to accelerate reliability stress testing of IC packaging during package development, qualification, and evaluation and reliability monitor programs [1]. Utilizing this approach in essence eliminates chip circuit failure mechanisms. Unlike packages with active die, in packages with the MDC die, when short occurred between two daisy-chain pairs of I/Os, there are four possibilities that can attribute to each pin of the two daisy-chain pairs. That makes the isolation of short failure difficult. Time Domain Reflectometry (TDR) is a well-described technique to characterize package discontinuity (open or short failure). By using a bare package substrate and a reference device, an analyst can characterize the discontinuity and localize it: within the package, the die-package interconnects, or on the die [2]. Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields generated by current. The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects [3]. In this paper, a new methodology that combines Resistance Analysis, TDR Isolation and SSM Identification for electrical debugging short in packages with the MDC die will be presented. Case studies will also be discussed.

In reliability test some chips suffered functional failure. Through a series of failure analysis experiments, the root cause was determined to be a silicon dislocation across LDD (Lightly Doped Drain) area causing p-n junction leakage. However, those failed samples all passed both CP (Chip Probe) and FT (Final Test) monitor. Therefore, it is reasonable to suspect that DVS (dynamic voltage stress) may enhance minor dislocations already existing before CP and FT. To prove this hypothesis, an experiment was designed to find the relationship between DVS and the depth of dislocation in silicon substrate. In conclusion, DVS could enhance dislocation across LDD area, which may induce reliability failure. Moreover, reliability concerns on this finding will be discussed in this paper.

Tower successfully completed a product qualification of its 130nm copper process this year. The key to this achievement was finding and eliminating a dominant failure mechanism, which appeared during HTOL stress. This paper will cover the failure analysis, in-line problem identification, and corrective actions taken that eventually lead to successful product qualification.

We investigated the degradation of device reliability due to Negative Bias Temperature Instability (NBTI) of PMOSFET on Strained Silicon on Insulator (S-SOI) substrates for the first time. The degradation has been found to be significantly higher for the S-SOI devices in comparison to SOI counterparts. Subsequent to a Constant Voltage Stress (CVS) during NBTI measurements, a negligible change in the subthreshold swing values was observed. Thus it is believed that generation of fixed charge is responsible for the observed BTI shift in threshold voltage (VTH) and transconductance (GM). Also higher BTI degradation was recorded for short channel devices.

In this paper, a case of package level reliability test failure was studied. A model of “Slice Defect”, which was identified as the root cause by failure analysis, is introduced. Experiment results are presented to approve that such model is in fact correct and the corrective actions are effective.

Stacked-die packaging was used to make an octal 20-bit analog-to-digital (A/D) converter by stacking two quad A/D converter die in a single 48-lead QFN (quad flat-pack, no leads) package. Reliability testing for product qualification initially failed only (biased) HAST test. Two failure mechanisms were identified. The first mechanism was silver ion migration at sensitive analog inputs due to high conductive die-attach fillets on the bottom die. The second mechanism was ILD delamination and passivation layer cracking due to spacer-attach stress on the surface of the bottom die. Electrical failure analysis was aided by a self test mode designed into the quad A/D converter. Package opening and other standard failure analysis techniques required some modification to accommodate the stacked-die package. This work points to critical stacked-die assembly steps, including conductive die-attach and nonconductive spacer-attach application, where effects of moisture, bias, and thermal stress must all be considered.