Air-assisted liquid cooling (AALC) has emerged as a preferred cooling solution for data centers housing traditional air-cooled server racks, owing to its straightforward integration with existing infrastructure. However, the rising power demands of AI hardware (30-100kW per rack) and its variable computational loads generate unprecedented heat levels that challenge system reliability and uptime. Through long-term reliability testing of AALC systems, we identify and analyze unique failure mechanisms associated with liquid cooling implementations. This paper presents our findings on system vulnerabilities, details the failure analysis methodology, establishes root causes, and outlines the corrective measures implemented to enhance AALC system reliability in high-performance computing environments.

This study investigates the application of 3D electron tomography to enhance transmission electron microscopy (TEM)-based failure analysis of 3D FinFET transistors. Traditional TEM analysis is challenged by projection effects due to the thickness of the sample, complicating accurate defect characterization in miniaturized semiconductor structures. The defects seen by conventional (2D projection) TEM imaging are unclear and difficult to interpret. Leveraging scanning transmission electron microscopy (STEM) and energy dispersive X-ray spectroscopy (EDS) tomography techniques, the study presents detailed examinations of two semiconductor samples exhibiting high leakage currents. Results reveal etched-out epitaxial regions subsequently filled with gate materials, critical for understanding device failure. By digitally reconstructing TEM lamellae in three dimensions, this approach overcomes projection artifacts and precisely localizes defects. The findings underscore the efficacy of 3D electron tomography in semiconductor failure analysis, offering insights crucial for improving device reliability and manufacturing processes in advanced semiconductor technologies.

Board level semiconductor reliability testing (BLTT) is a crucial step in the product development life cycle of modern electronics. While the primary focus of semiconductor reliability historically has been to understand the robustness of the solder joint, there are other aspects of the semiconductor package which are also susceptible to failure after the product has been assembled. Despite its overwhelming importance, there is no one centralized resource outlining best practices for conducting BLRT across industries. Fortunately, industry standards do exist. Among them are outlines for conducting tests including temperature cycling, mechanical shock, humidity dwell among others. In this work we present a case study exploring some of the unique challenges and methods associated with conducting BLRT using mechanical shock testing. Namely, we discuss the practical challenges of conducting these tests in the presence of a constant noise source and performing die level failure analysis on components suffering from warpage while back side films (BSFs) are applied as a protective coating on the package.

This paper describes a backside approach methodology for sample preparation, fault localization and physical defect analysis on p-GaN power HEMT electrically stressed in DC voltage surge and AC switching mode. The paper will show that preparation must be adapted according to the defect position (metallurgy, dielectric layers, epitaxy, etc.) which depends on the type of stress applied. In our life-operation mode amplified electrical stress reliability study, the failure analysis will help us to reveal the weakest parts of the transistor design in relation to the type of applied stress. The failure analysis presented in this paper is composed of electrical characterization, defect localization with PEM and LIT, FIB Slice&View, TEM analysis and frontside conductive AFM after a deep HF.

Atom probe tomography is used to characterize the 3D Al dopant distribution within the gate diffusion region of a deconstructed SiC n-channel junction field effect transistor. The data reveals extensive inhomogeneities in the dopant distribution, which manifests as large Al clusters - some of which are ring-shaped and indicative of dopant segregation to lattice defects in the SiC. The presence of defects in the SiC is confirmed by transmission electron microscopy of an identical region. Factors that may impact the atom probe data quality and consequently complicate data interpretation are considered, and their severity evaluated. The possible origin of the lattice defects in the SiC and the corresponding implications for device performance and reliability are also discussed. Overall, the utility of atom probe tomography and correlative transmission electron microscopy for revealing potential failure mechanisms of next-generation semiconductor devices is demonstrated.

Presentation slides for the ISTFA 2023 Tutorial session “Reliability and Failure Analysis of SiC Power Devices and Modules.”

The high temperatures and thermal cycling experienced by integrated circuit packages can induce warpage that in turn can lead to cracks developing at material interfaces that compromise the integrity of electrical traces within the device. In this study, the authors demonstrate how Electro-Optical Terahertz Pulsed Reflectometry (EOTPR) with dynamic temperature control can be used to localize and characterize the resistive faults created by such thermally induced cracks. The EOTPR technique provides quick, reliable, and accurate results, and it allows automatic probing that can be used to generate defect maps for further root cause analysis. The approach demonstrated in this paper shows the significant potential of EOTPR in soft failure characterization and in failure and reliability analysis.

Currently, wire bonding is still the dominant interconnection mode in microelectronic packaging, and epoxy molding compound (EMC) is the major encapsulant material. Normally EMC contains chlorine (Cl) and sulfur (S) ions. It is important to understand the control limit of Cl and S in the EMC to ensure good Au wire bond reliability. This paper discussed the influences of Cl and S on the Au wire bond. Different contents of Cl and S were purposely added into the EMC. Accelerated reliability tests were performed to understand the effects of Cl, S and their contents on the Au wire bond reliability. Failure analysis has been conducted to study the failure mechanism. It is found that Cl reacted with IMCs under humid environment. Cl also caused wire bond failure in HTS test without moisture. On the other hand, the results showed that S was not a corrosive ion. It was also not a catalyst to the Au bond corrosion. Whilst, high content of S remain on the bond pad hindered the IMCs formation and caused earlier failure of the wire bond.

As devices shrink, mitigating off-state power consumption has become a major concern for dynamic random access memory (DRAM) product development. The interface trap induced reduction of the retention time of DRAM cells has become increasingly critical due to aggressive device shrinkage. In this paper, the influence of reliability evaluation after device manufacturing on the number of interface traps in buried-channel-array-transistors and the optimal H 2 annealing temperature were investigated for the reduction of trap-induced leakage currents that cause retention time degradation in DRAM cells. This study is expected to solve the problem of retention time and off-state power consumption caused by interface traps and to be utilized as a cornerstone for next-generation DRAM development.

Traditionally, reliability defects are addressed by end-of-line electrical measurements and extensive and dedicated testing during packaging. These tests cover almost every known defect condition and ensure product reliability with high confidence, but they occur in the final stage of manufacturing and are quite time intensive. This paper shows that inline reliability metrology based on Raman spectroscopy is an effective approach for early fault detection and can be used to monitor unintended epi growth, strain, lattice defects, stacking faults, dislocations, and post-etch residues. It can also reveal process anomalies and potential material problems. The paper examines the relationship between process parameters and reliability and reviews the enablers of preventive, early-detection inline metrology in the fab.

A typical workflow for advanced package failure analysis usually focuses around two key sequential steps: defect localization and defect characterization. Defect localization can be achieved using a number of complementary techniques, but electro optical terahertz pulse reflectometry (EOTPR) has emerged as a powerful solution. This paper shows how the EOTPR approach can be extended to provide solutions for the growing complexity of advanced packages. First, it demonstrates how localization of defects can be performed in traces without an external connection, through the use of an innovative cross-sectional probing with EOTPR. Then, the paper shows that EOTPR simulation can be used to extract the interface resistance, granting an alternative way of quantitative defect characterization using EOTPR without the destructive physical analysis. These novel approaches showed the great potential of EOTPR in failure analysis and reliability analysis of advanced packaging.

Redistribution layer (RDL) bonding pad over active circuitry is utilized to re-route the original bond pad to other location for wire bonding using RDL. The damages in the active circuitry beneath the RDL bond pad induced by stress from wire bonding and package must be evaluated for reliability in the product development. The experimental approach and test structures are proposed in this paper. Functional fail was detected in electrical test after reliability tests on packaged IC. The dielectric cracking initiated by wire bonding that corresponds to the functional fail is identified by physical failure analysis and Transmission-Electron-Microscopy (TEM) at a specific location beneath the RDL bond pad. Finite element simulations are used to analyze the wire bonding stress distribution and circuit-under-pad design effect. The predicted maximum stress for the dielectric cracking matches to the location observed in the physical failure analysis. Based on the experiment and the simulation data, design rules for the circuit routing beneath the RDL bond pad have been successfully developed that all product reliability tests pass later with extend bonding power. The results lead to significant improvements in the robustness of circuit routing structure beneath the RDL bond pad for dielectric cracking without modifications of the existing processes for the product.

Reliability tests, such as Time-Dependent Dielectric Breakdown (TDDB), High-Temperature Operating Life (HTOL), Hot Carrier Injection (HCI), etc., is required for the lifetime prediction of an integrated circuit (IC) product. Those reliability tests are more stringent and complex especially for automotive Complementary Metal–Oxide–Semiconductor (CMOS) devices, this because it involves human lives and safety. In foundries failure analysis (FA), Transmission Electron Microscopy (TEM) analysis often required in order to provide insights into the defect mechanisms and the root cause of the reliability tests. In this paper, application of high resolution Nano-probing Electron Beam Absorbance Current (EBAC), Nano-probing active passive voltage contrast (APVC), and TEM with Energy Dispersive X-Ray Spectroscopy (EDX) to identify the failing root cause of Inter- Poly Oxide (IPO) TDDB failure on an automotive grade Non- Volatile Memory (NVM) device was investigated. We have successfully demonstrated that TEM analysis after Nanoprobing EBAC/APVC fault isolation is an effective technique to reveal the failure root cause of IPO breakdown after reliability stresses.

This paper presents Electrical Failure Analysis (EFA) and Physical Failure Analysis (PFA) on a random time zero (t0) gate oxide defect within an IBM processor manufactured with a 14nm SOI (Silicon On Insulator) FinFET technology. The natures of the Functional Fail, the gate oxide defect, and the transistor characteristics are included. The impact of this gate oxide defect to product yield and performance, plus the extent to which it extends across the product chip, which includes passing circuits, is covered. Since chips, which may contain this defect, could be present within the entire product lifecycle, the reliability aspects of the defect at the transistor level were investigated. Among the various reliability stresses available for transistors, Constant Voltage Stress (CVS) Bias Temperature Instability (BTI) was chosen. CVS BTI stressing was able to be performed on both the NFETs and PFETs within the Inverter of the failing circuit, plus other identical reference circuits. The BTI stress nanoprobing is covered. This includes an overview of BTI stressing, confirming the nanoprobing system and electrical stress/test programs are adequate for BTI stressing, BTI stress methodologies for Inverters, plus the BTI stress results. The transistor level BTI stress results are discussed and compared to other published BTI literature. Finally, the reliability aspects of this gate oxide defect are discussed.

Compared with space parts, consumer parts are highly functional, low cost, compact and lightweight. Therefore, their increased usage in space applications is expected. Prior testing and evaluation on space applicability are necessary because consumer parts do not have quality guarantees for space application [1]. However, in the conventional reliability evaluation method, the test takes a long time, and the problem is that the robustness of the target sample can’t be evaluated in a short time. In this report, we apply to the latest TSOP PEM (Thin Small Outline Package Plastic Encapsulated Microcircuit) an evaluation method that combines preconditioning and HALT (Highly Accelerated Limit Test), which is a test method that causes failures in a short time under very severe environmental conditions. We show that this method can evaluate the robustness of TSOP PEMs including solder connections in a short time. In addition, the validity of this evaluation method for TSOP PEM is shown by comparing with the evaluation results of thermal shock test and life test, which are conventional reliability evaluation methods.

NCF (Non Conductivity Film) is a material used for under-fill purpose in the TSV (Through Silicon Via) process, and is a key material for ensuring TSV 3D Package (PKG) reliability. Among the types of defects generated by the NCF, the most typical type is delamination. Particularly in NCF delamination frequently occurs during reliability test, we analyzed chemical state change of NCF according to reliability test step/condition by utilizing FTIR and TMA. Through these studies, we clarify the cause of Delamination.

The degraded performance of a power MOSFET affects customer system reliability and consumer perceptions of quality. Building a reliable product and associated application specific lifetime models to predict the suitability of a power device for a given solution can enable competitive advantages, increased quality, enhanced performance and result in market share gains. This paper describes the methodology employed to configure an application specific reliability test, the failure rates and modes observed, the package modelling, and design improvements implemented. The validation of such relative to its original form and competitor products is discussed where we demonstrate a doubling in performance and an approximate 50% increase in current handling capability. This type of analysis and application specific approach to innovation enables one to focus design improvements in areas most relevant to customer concerns while at the same time adding credibility to specified product limits.

X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

Fault isolation is the most important step for Failure Analysis (FA), and it is closely linked with the success rate of failure mechanism finding. In this paper, we will introduce a case that hard to debug with traditional FA skills. In order to find out its root cause, several advanced techniques such as layout tracing, circuit edit and Infrared Ray–Optical Beam Induced Resistance Change (IR-OBIRCH) analysis had been applied. The circuit edit was performed following layout tracing for depositing probing pads by Focused Ion Beam (FIB). Then, IR-OBIRCH analysis with biasing on the two FIB deposited probing pads and a failure location was detected. Finally, the root cause of inter- metal layer bridge was found in subsequent physical failure analysis.

Destructive physical analysis (DPA) is one of the reliability evaluation methods, which observes defects and faults in a device, and it can classify the reliability level of the device. After a description of the current method for Au wires, this paper explains the DPA for a Cu wire device. The DPA for semiconductor devices is divided roughly into three steps: a non-destructive inspection, an assembly process inspection, and a wafer process inspection. Investigation of DPA for Cu wire device includes wire material identification, optimization of decapsulation for Cu wire device and wire pull strength test, and observation of package cross-section. From the result, novel sample preparation (embedding a sample in molding package and forming the package to be suitable for cross-sectional observation by ion polishing) enables the observation of the thin alloy layer at the wire/pad interface.