This presentation covers the basic physics needed to understand and to effectively apply backside IC analysis techniques to flip-chip packaged die. It describes the principles of light transmission through silicon and the factors that influence optical image formation from the backside of the wafer or die. It also provides information on the tools and techniques used to expose surfaces, regions, and features of interest for analysis. It describes the steps involved in CNC milling, mechanical grinding and polishing, reactive ion etching (RIE), laser microchemical (LMC) etching, and milling and etching by focused ion beam (FIB). It explains where and how each technique is used and quantifies the capabilities of different combinations of methods.

This presentation covers the basic physics needed to effectively apply backside IC analysis techniques to flip-chip packaged die. It describes the principles of light transmission through silicon and the factors that influence optical image formation from the backside of the wafer or die. It also provides information on the tools and techniques used to expose surfaces, regions, and features of interest for analysis. It describes the steps involved in CNC milling, mechanical grinding and polishing, reactive ion etching (RIE), laser microchemical (LMC) etching, and milling and etching by focused ion beam (FIB). It explains where and how each technique is used and quantifies the capabilities of different combinations of methods.

This paper explains the CLSM technique and presents surface roughness measurement data from several groups of known authentic and suspect counterfeit parts. Surface roughness is an important characteristic of plastic encapsulated or metal lidded parts because counterfeit parts are often blacktopped or re-polished and remarked.

Presence of foreign materials (i.e, contamination) can affect the reliability of copper (Cu) bumps when it affects the wettability of the solder and consequently weakens the joint formation of the copper to the substrate. This paper looks at a case of non-wetting of Cu bumps due to silicon contamination induced during assembly processing. In this case study, surface roughness is the main factor being altered when foreign materials contaminate the metal substrate. Sample devices were tested in a resistive open unit and a direct current failing unit, respectively. It was found that the silicon dust present on the substrate in effect "roughens" the surface, thereby decreasing the wettability between the molten solder to the metal substrate. For future studies, it is recommended that the effect of reliability stress activities on the Cu bumps with silicon contaminations be examined to evaluate the risks for possible field failures of this defect.

Direct surface bonding of wafers in 3D integration requires perfectly smooth surfaces, with roughness values below 1 nm, usually characterized with Atomic Force Microscopy. An alternative technique, Digital Holography Microscopy is evaluated here and shown to be precise enough to differentiate adequate wafers, that is chemical mechanical polished, from non treated ones.

High frequency signal propagation through transmission lines has been an important discipline for RF engineers. With advancements in digital technologies, especially when data rates reached multiple Gb/s, package designers have to consider parameters such as transmission loss and trace impedance in order to maintain signal integrity. For high frequency signals, the surface roughness of the copper trace becomes increasingly significant in determining conduction loss, due to current confinement to the conductor surface by the skin effect. Accurate 3D conductor surface maps are required for correct trace insertion loss simulation. Practical methods for package trace exposure and 3D surface height map acquisition are discussed in this paper. Advantages and disadvantages of these methods, and their implementation to real packages are shown. Using electrical parameters resulting from a 3D trace surface map, the error between electrical simulations and actual measurements of insertion loss in an FCBGA package have been reduced from 6% to nearly zero, enabling tighter margins in 10GB/s high speed serial design.

The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.

The geometries of several proposed new electronic device structures put constraints on the size of the AFM images that can be obtained in the gate areas. The images that can be obtained on these structures are of a significantly smaller area, at a much higher resolution, than is typically measured. The analysis areas are limited to ~ one-tenth of what is normally scanned. The micro-roughness and feature size information contained in AFM measurements changes with scan size. Care must be taken when introducing such a dramatic change in the measurements being made. Several factors should be considered to determine an appropriate sampling plan and select a proper reference set for these high-resolution measurements. In this paper, several of these factors are discussed in the context of determining a sampling plan and reference targets for sidewall micro-roughness of fins that allow 50 nm analysis areas.

In the selection of ultra low k materials, process compatibility is a very important factor. Plasma processing plays a critical role in enhanced interconnect integration. It is therefore important to study plasma interaction with the ultra low k materials and its effects on the structure and property of these materials. X-ray reflectivity (XRR) measurement can be used to measure film thickness, density and interface roughness, which are important parameters to check for after plasma treatments. In the current study, porous SiLK (p-SiLK) was treated with various plasmas, such as O2, O2/N2, H2/N2, CH2F2/Ar and CF4/O2. XRR results indicate that the density of the p-SiLK films remains unchanged after various plasma treatments. Surface roughening occurs during the plasma treatments, accompanied by the decrease in film thickness. Plasma-induced surface roughening was also observed using atomic force microscope (AFM). Such roughening is more severe for plasma treatments using oxygen-containing plasmas. FTIR analysis indicates that the chemical structure of the p-SiLK films is not significantly affected by plasma treatment. It is reasonable to conclude that oxidation of the surface plays a major role in the plasma-induced change in surface roughness and film thickness.

An increasing number of analysis techniques requires access to the backside silicon of a functional device. For backside sample preparation of packaged devices, CNC milling tools can perform both package opening and circuit preparation. They offer good versatility in terms of type and size of packages – from ceramic to exotic plastic molding. They are suited for precise silicon thinning as well as polishing. Finally, the automation and software control of the process offer good reproducibility of chip opening and preparation. For some applications, the silicon substrate needs to be thinned as closely as possible to the circuitry with a uniform thickness (less than 100 microns). Bent silicon surfaces are challenging for backside sample preparation. This is the case of C4 packages or large plastic TSOP packages. Conventional approaches would cut off the top of the bent surface. From small flat surface to large bent silicon dies, we will detail our technique for thinning silicon to a uniform thickness with extreme precision. Finally, we will characterize the final surface roughness which plays an important role in backside techniques.

Ever since the invention of the scanning acoustic microscope (SAM), a key objective has been the enhancement of the resolution in an interior image. Thus, an acoustic lens that can form an interior image with a shear wave has been designed. The use of this lens gives benefits such as an increase of lateral resolution in the interior image, a reduction in background noise caused by surface roughness, and a reduction of spherical aberration. Significantly, with the current trend towards microminiaturization of microelectronic packages, acoustic microscopy with higher resolution and removal of surface roughness can play an important role in diagnostic examinations and failure analysis. In this paper, applications for the lens in microelectronic IC packages will be summarized.

For conventional photoemission microscopy the silicon is thinned to a few tens of micrometres for backside imaging since silicon is opaque in the visble part of the spectrum. However, at wavelengths greater than approximately 1050 nm, most silicon is effectively transparent. Hence, the use of an infrared photoemission microscope (IRPEM) operating at wavelengths of 1100 to 2500 nm, usually eliminates the need for thinning, except where the silicon is heavily doped. However, the plastic encapsulation of packaged devices must be removed and the die surface polished. A polishing system has been evaluated and optimised for this purpose. Surface roughness (Ra) of 1 nm or better was obtained. Representative applications are shown and discussed.

This article deals with an investigation to determine the root cause of the differences noted in the fatigue test data of main rotor spindle assembly retaining rods fabricated from three different materials. The US Army Research Laboratory - Materials Directorate (ARL) subjected the failed tie rods to visual examination and light optical microscopy and then performed dimensional verification and measured the respective surface roughness of the rods in an effort to identify any discrepancies. Next, mechanical testing (hardness, fatigue, and tensile) was performed, followed by metallography, and chemical analysis. Finally, the ARL performed laboratory heat treatments at the required aging temperature. The results suggested that the difference in performance could not be directly linked to chemical composition, dimensional intolerance, surface roughness or any metallographic variance and that the likely explanation for the difference observed in the mechanical performance of materials lies within a variation of the heat treatment.