Soft defects—failures that manifest only under specific voltage, temperature, or frequency conditions—require specialized fault isolation techniques for accurate characterization. This paper demonstrates thermal response failure localization using scanning electron microscope (SEM) nanoprobing with an integrated thermal stage. While nanoprobing typically serves as the final step in fault isolation failure analysis (FIFA), thermal nanoprobing is essential for characterizing temperature-dependent parametric defects by enabling measurements at both passing and failing temperatures. We present three case studies: a "worse at cold" failure reproduction, a parametric root cause identification through thermal characterization, and a complex thermal failure that was uniquely isolatable through thermal nanoprobing. These cases illustrate the technique's effectiveness in analyzing temperature-dependent defects that occur outside room temperature conditions.

Photoresist (PR) profiles tend to have deformation and shrinkage with typical transmission electron microscopy (TEM) sample preparation methods using a focused ion beam scanning electron microscope (FIB-SEM). As the temperature increases during the TEM sample preparation, it may lead to deformation and shrinkage in PR profiles. In this study, we analyze the impact when performing the sample preparation at a cold temperature using a cryo-FIB to minimize deformation and shrinkage issues. To test this methodology, the TEM sample preparation process was performed under different conditions. From these experiments, the TEM results with full cryo conditions showed that the PR line to space ratio was closest to the target, which is the sample’s real line to space ratio (1:1), and the bottom anti-reflective coating (BARC) shrinkage was minimized.

This presentation provides an overview of lock-in thermography and its application in semiconductor failure analysis. It begins with a review of direct thermal imaging, IR transmission and detection, and the fundamentals of lock-in measurements. It compares and contrasts steady-state IR imaging with lock-in thermography and shows how lock-in frequency and the shape of the excitation signal can be varied to increase signal-to-noise ratio and reduce acquisition time, thereby exposing a wider range of defects. It also presents several case studies in which lock-in thermography is used to diagnose shorts and hot spots in packaged devices, electronic systems, and 3D assemblies.

This presentation is a pictorial overview on the implementation of lock in thermography, the various types of images that can be obtained, and the interpretation of the results. It also includes a refresher on the use of discrete Fourier transforms (DFT) in signal processing.

Dynamic analysis by laser stimulation (DALS) is a method used to analyze temperature-dependent failures. There are cases, however, where the laser alone cannot get devices hot enough to induce an observable change in behavior. This paper examines three such cases and describes how analysts were able to induce and diagnose the underlying failure by using external signals, complex triggering, and resistive heating to compensate for limitations in laser power.

Temperature-dependent die warpage measurements show the possibility to analyze the thermomechanical behavior during assembly, e.g. within soldering processes. The warpage data acquisition is realized by confocal chromatic white light profilometry in combination with a precision heating/cooling chuck encapsulated in a chamber with optical access. The combination of these two tools allows precise die warpage evaluation under varied device temperature up to +400°C. This method helps to solve emerging challenges due to warpage during assembly of state of the art packages including thin dies and stacked dies as in e.g. 3D-SIPs.

This paper provides a detailed analysis on the optical detection of temperature effects in FinFETs via (spectral) photon emission microscopy (SPEM/PEM) with InGaAs detector and electro-optical frequency mapping (EOFM, similar to LVI) for 14/16 nm Qualcomm Inc. FinFETs. It analyzes physical parameters of the FinFETs such as electron temperature and the relation between signal curve and operating condition of the device by photon emission slopes and spectra. The paper also traces device self-heating effects within the FinFETs by means of EOFM signal courses. With EOFM it was possible to detect self-heating effects of the FinFETs providing a further method to estimate device and substrate heating. Results showed that it is possible to obtain valuable device parameter information (for example, electron temperatures and self-heating) via optical investigations (PEM/ EOFM), which are not accessible electrically in modern integrated circuits. This information adds further details to device reliability and functionality approximations.

Aluminum-copper alloys are popular for many applications that take advantage of the combination of properties in the alloys. This paper describes the use of multiple advanced failure analysis tools to analyze the physical and chemical properties of Al-Cu alloy thin films.

Ni(5 at.%Pt ) films were silicided at a temperature below 400 °C and at 550 °C. The two silicidation temperatures had produced different responses to the subsequent metal etch. Catastrophic removal of the silicide was seen with the low silicidation temperature, while the desired etch selectivity was achieved with the high silicidation temperature. The surface microstructures developed were characterized with TEM and Auger depth profiling. The data correlate with both silicidation temperatures and ultimately the difference in the response to the metal etch. With the high silicidation temperature, there existed a thin Si-oxide film that was close to the surface and embedded with particles which contain metals. This thin film is expected to contribute significantly to the desired etch selectivity. The formation of this layer is interpreted thermodynamically.

Two cases of high temperature failure analyses are presented. In both cases an on-chip “heater” – power MOSFET was used to achieve high temperature for both global fault isolation and block/transistor level nodal analysis. The “heater” provides a quick and effective way of changing the device temperature without significantly modifying the bench setup. In both cases, the results show improved probability of successfully isolating the fail site, by performing OBIRCH analysis and nodal analysis.

The temperature and strain rate effects on the shear properties of selected Pb-free solders were investigated. The experiments were performed using single lap shear specimens. All testing was performed using a standard tensile test metrology. The following results were found: 1) Sn-3.5 wt.% Ag outperformed all the other solders in terms of its mechanical strength at all test conditions due to the formation of Ag3Sn precipitates in the bulk solder and Cu6Sn5 intermetallic formation along the interface. However, ductility was sacrificed as this solder strain hardens. 2) The strength and ductility of the solder joint is strongly dependent on the test temperature and strain rate. Data in this work reflects a decrease in strength and ductility when the test temperature is increased. This phenomenon can be attributed to the increase in energy as temperature is increased to overcome dislocation barriers such as impurities and grain boundaries that impede the motion of dislocation. When strain rate is increased, the amount of plastic deformation experienced by the solder increases and more dislocations are formed. Due to the increase in proximity and number of the dislocations, the net result is that motion of the dislocations are hindered thus requiring more stress to deform the material.

The need for high bandwidth, high speed interconnects with optimum routing through computer backplanes has led to the use of optical interconnects in multiprocessor computing systems [1]. Most of the current commercially available optical interfaces are based upon 850nm vertical-cavity surface-emitting lasers (VCSELs). Extensive studies conducted by the VCSEL manufacturers show that the reliability of these devices continues to improve [2-4]. In order to understand the risks and implications of using VCSELbased modules in computer systems, we have conducted an experiment designed to provide insight into the emission degradation and failure of VCSEL devices. In this paper we briefly describe the experiment and review the results of the subsequent failure analysis on degraded VCSEL arrays.

This article discusses the techniques useful in the failure discovery process in PC motherboard. It discusses the application of infrared (IR) camera in failure analysis, which overcomes time consumption problems. The article focuses on the experience gained from nine different case studies, where IR thermography system was used to both measure relative temperatures as well as absolute temperatures of components. The failures investigated are overdriven components, finding end-of-life but still functional components, correctly specified components with quality defects, incorrect component placement, internal voltage common collector to ground low resistance integrated circuits failures, PCB defects resulting in power to ground failures, soldering defects resulting in lead opens or solder bridges, and copper trace manufacturing defects or stress-induced cracks.

A number of backside analysis techniques rely on the successful use of optical beams in performing backside fault isolation. In this paper, the authors have investigated the influence of the 1340 nm and 1064 nm laser wavelength on advanced CMOS transistor performance.

This paper describes Scanning Electron Acoustic Microscopy (SEAM) applications, particularly to samples that are of interest to the microelectronics industry. Several applications of SEAM involving semiconductor and ferroelectric samples are discussed in this paper. The expanding scope of applications for SEAM presents exciting possibilities. The challenge ahead lies in understanding the contrast mechanisms in SEAM signal formation as well as correlating results to the physical properties of samples.

A model has been developed accurately predicting the temperature along a length of wire heated by passing a current through it. The wire is modeled as a transmission line with its thermal properties mapped onto the appropriate electronic analogs. A program describing the model circuit has been written in PSPICE such that time versus temperature curves can be generated for any wire given the material, diameter, length, and stressing current. The model has been dynamically temperature corrected, and its accuracy has been demonstrated for two types of fuses and one type of bond wire. This model is useful for predicting fusing conditions of fuse elements or bond wires, assessing the reliability of a material for given operating conditions (by knowing the temperature the material would attain), derating for design, and as a failure analysis tool by providing insight into an overstress condition in which a wire has melted open.