Infrared lock-in thermography systems are frequently utilized for non-destructive failure analysis of integrated circuits due to sensitivity of the thermal detector to small temperature changes from electrical activity. This thermal sensitivity can also be leveraged for design verification and debug of device thermal management via absolute temperature mapping. The application of temperature mapping to a device under test (DUT) that requires boards and sockets, such as in tester based applications, has traditionally been challenging, due to the requirement that the DUT not be moved and the difficulty of heating the DUT through the thermal mass of the boards and sockets to which the DUT is mounted. This paper describes a proposed alternative single-temperature in-situ calibration method to eliminate the need for a heated thermal chuck for absolute temperature mapping. Preliminary results are promising and show that the new alternative single-temperature in-situ method results in temperature measurements within 1 °C close to room temperature and within 2.5 °C at elevated temperatures up to approximately 75 °C, as compared to the 1 °C accuracy of the current standard two-temperature in-situ method. While this alternate method is not as accurate as the standard two-temperature in-situ calibration method, the fact that it can be performed at a single room temperature means that it enables absolute temperature mapping for use cases requiring boards or socketed DUTs, as is the case for tester applications. An example characterization of a DUT utilizing varying clock signal inputs shows the added flexibility and ease of setup that the alternative single-temperature workflow brings, creating new opportunities for use-cases such as boards and testers where the use of a heated thermal chuck is not viable.

While 2.5D and 3D solutions continue to drive advancements in the electronics packaging industry, challenges persist with their reliability and qualification. In this paper, we introduce a new technique that may prove valuable for nondestructive, in-situ measurements of package and die warpage. This system allows for the powerful visualization tools of Computed Tomography to be applied to samples at elevated and cryogenic temperatures over a broad temperature range (+125C to -257C).

Lock-in thermography (LIT) is a firmly established and powerful technique for IC defect localization. The standard approach is to detect and analyze the device temperature fluctuation between two bias conditions using an infrared thermal imaging camera and check for any anomalous heat response. For the most straightforward setup, these bias conditions would be achieved by the modulation of a supply voltage provided by the LIT system. This allows for synchronization to the internal camera frame rate. In addition to this method, the ability to provide an external trigger may be an option, as it is for the ELITE system by Thermo Fisher Scientific. This expands the LIT arena to failures that may only be observable by, for example, setting different register contents at a constant supply voltage. Though IC testers can be used to provide the stimulus and a trigger signal for these situations, often a simpler, more compact solution would be beneficial for the failure analyst. This paper presents such an alternative: the application of a low-cost, USB-based module which can emulate various communication protocols (for example, I 2 C, SPI) while providing a synchronized timing pulse to externally trigger the ELITE, thus facilitating dynamic LIT investigations. The efficacy of this solution is demonstrated by a case study in which dynamic LIT produced a single hot spot at the defect site that was undetected by the voltage modulation approach.

Failure analysis engineers apply a combination of conventional static fault isolation tools such as OBIRCH, PEM, or lock-in thermography (LIT) to detect simple short defects. However, if the defect is located in a complex circuit, analysis can be more challenging. Laser voltage probing and imaging (LVx) is widely used but will have difficulty in localizing a defect in the backend layers. The combination of LVx and LIT can resolve complex short cases that either of these techniques alone cannot easily do. This paper introduces the thermal effect of LVx and applications of LIT for functional analysis, and it describes and provides case histories for complementary fault isolation procedures for detecting defects in metal layers and transistors.

This presentation provides an overview of photonic measurement techniques and their use in isolating faults and locating defects in ICs. It covers transmission, reflectance, and absorption methods, describing key interactions and important parameters and equations. Reflectance methods discussed include electro-optical probing (EOP), electro-optical frequency modulation (EOFM), and laser-voltage imaging (LVI). Absorption methods covered include those based on the absorption of light in semiconductors, as in optical beam induced current (OBIC), light-induced voltage alteration (LIVA), and laser-assisted device alteration (LADA), and those based on absorption in metals, as in thermally induced voltage alteration (TIVA), optical beam induced resistance change (OBIRCH), and thermoelectric voltage generation or Seebeck effect imaging (SEI). The presentation also covers thermoluminescence (lock-in thermography) and electroluminescence (photon emission) measurement methods and assesses hardware security risks posed by current and emerging photonic localization techniques.

This presentation provides an overview of lock-in thermography and its application in semiconductor failure analysis. It begins with a review of direct thermal imaging, IR transmission and detection, and the fundamentals of lock-in measurements. It compares and contrasts steady-state IR imaging with lock-in thermography and shows how lock-in frequency and the shape of the excitation signal can be varied to increase signal-to-noise ratio and reduce acquisition time, thereby exposing a wider range of defects. It also presents several case studies in which lock-in thermography is used to diagnose shorts and hot spots in packaged devices, electronic systems, and 3D assemblies.

This presentation is a pictorial guide to the selection and application of measurement methods for defect localization. The presentation covers passive voltage contrast (PVC), nanoprobing, conductive atomic force microscopy, and photon emission microscopy (PEM). It describes signal types, how the measurements are made, the sensing mechanisms involved, and the output that can be expected.

This presentation is a pictorial overview on the implementation of lock in thermography, the various types of images that can be obtained, and the interpretation of the results. It also includes a refresher on the use of discrete Fourier transforms (DFT) in signal processing.

This presentation covers the challenges associated with IC package inspection and shows how two nondestructive techniques, scanning acoustic microscopy and X-ray imaging, are being used to locate and identify a wide range of defects, particularly those in 3D packages and multilayer boards. It reviews the basic principles of scanning acoustic microscopy (SAM), X-ray imaging, and 3D X-ray tomography and the factors that affect image resolution and depth. It demonstrates the current capabilities of each method along with different approaches for improving resolution, contrast, and measurement time.

Lock-In Thermography is an established nondestructive method for analyzing failures in microelectronic devices. In recent years, a major improvement made it possible to acquire time-resolved temperature responses of weak thermal spots, greatly enhancing defect localization in 3D stacked architectures. One limitation, however, is in the method used to determine defect depth, which is based on the numerical estimation of the delay between excitation and thermal response inferred from the value of the lock-in phase. In structures where the region between the origin of the defect and sample surface is partially or fully transparent to infrared signals, interference between radiated and conducted signal components largely falsifies the phase value on which the classical depth estimation relies. In the present study, blind source separation based on independent component analysis was successfully used to separate interfering signal components arising from direct thermal radiation and conduction, resulting in a precise estimation of the defect depth.

This article describes a method that combines Analog Signature Analysis (ASA) with IR based Direct Current Injection (IRDCI) for printed circuit board assembly failure analysis. The integration of ASA extends the diagnostic capability of IRDCI from shorted power rails to any measurement location that shows signature differences. It also facilitates the detection of electrical breakdown or degradation without having to remove suspected faulty components from the board.

This paper describes a project to develop and deploy a systematic screening methodology involving computed tomography (CT) to inspect a set of electromagnetic interference (EMI) filter components for a spacecraft application. The goal was to deploy the nondestructive CT test to replace the destructive test method typically deployed for such components. The paper describes the development of test criteria, fixturing, inspection process, and data analysis, including quantitative image analysis of voids and cracks. The initial results indicated that the parts would not pass the requirements established in the test design. A waiver was written to the project clarifying that if the parts were to be used in the assembly, they should be considered as simple conductors with EMI filtering capability viewed as an added benefit rather than a guaranteed design requirement.

This paper demonstrates a novel defect localization approach based on EBIRCH isolation conducted from the backside of flip chips. It discusses sample preparation and probing considerations and presents a case study that shows how the technique makes it possible to determine the root cause of subtle defects, such as bridging, in flip chip failures.

Thermal hotspot (THS) fault isolation is an effective technique for detecting heat-generating failure modes, especially those involving excessive current or resistance. The normal approach for modulation mode THS analysis is to connect a power supply to the leakage pin of the device under test through the modulation switch on the instrument. There are instances, however, where this may not work. This paper discusses two such cases: one in which the output terminal of the modulation switch is connected to the failing device through a series resistor in order to limit current, and one where a voltage divider is used to connect the unit under test to the modulation switch in order to create ramping sequences that mimic IQ current spikes for THS analysis.

An image sensor module failed in the field and was returned showing functional issues and a supply-to-ground short. After the hard lens mounted over the imaging chip was removed, the short disappeared along with the functional issues. This paper explains how the authors were able to restore the failure mode and discover the underlying defect, via backside focused ion beam cross-sectioning, with minimal intrusion into the top-side package and silicon.

This paper explains how the authors determined the cause of a fast-to-rise failure discovered during scan chain testing of an image sensor. The failed device was mounted on a portable card that facilitates transfer between test platforms in an electro-optical probing (EOP) system. Initial fault localization was conducted through backside PEM, but the results were inconclusive. The part was then analyzed on a digital scan chain tester to check for flaws in the daisy chain of shift registers. Through broken scan chain analysis, the potential cause of the problem (a failing flip-flop) was narrowed down to a few chain links and ultimately pinpointed using EOP fault isolation techniques. The failed device was then deprocessed by parallel lapping and analyzed in a SEM, revealing a broken poly gate as the physical cause of failure.

This paper presents a die-level sample preparation technique that uses selective etch chemistry and laser interferometry to expose the entire top metal layer surface for electrical fault isolation. It also describes a novel e-beam based probing technique called StaMPS which is used to isolate logic structure failures through SEM image contrasts. By landing SEM probe tips on exposed metal pads and controlling logic states via an applied bias, different levels of contrast are created highlighting structural failure locations. Die-level sample preparation combined with e-beam fault isolation optimizes turnaround time by delayering die in less than an hour and by locating several types of defects in a single sample.

This presentation provides an overview of photonic measurement techniques and their use in isolating faults and locating defects in ICs. It covers transmission, reflectance, and absorption methods, describing key interactions and important parameters and equations. Reflectance methods discussed include electro-optical probing (EOP), electro-optical frequency modulation (EOFM), and laser-voltage imaging (LVI). Absorption methods covered include those based on the absorption of light in semiconductors, as in optical beam induced current (OBIC), light-induced voltage alteration (LIVA), and laser-assisted device alteration (LADA), and those based on absorption in metals, as in thermally induced voltage alteration (TIVA), optical beam induced resistance change (OBIRCH), and thermoelectric voltage generation or Seebeck effect imaging (SEI). The presentation also covers thermoluminescence (lock-in thermography) and electroluminescence (photon emission) measurement methods and assesses hardware security risks posed by current and emerging photonic localization techniques.

This presentation is a pictorial guide to the selection and application of measurement methods for defect localization. The presentation covers electron beam absorbed current (EBAC), electron beam induced current (EBIC), passive voltage contrast (PVC), optical and electron beam induced resistance change methods (OBIRCH and EBIRCH), lock-in thermography, photon emission microscopy (PEM), and nanoprobing. It describes how the measurements are made, the sensing mechanisms involved, and the output that can be expected.

The paper demonstrates accurate fault isolation information of metal-insulator-metal (MiM) capacitor failures by lock-in thermograph (LIT). In this study, a phase image spot location at a lock-in frequency larger than 5 Hz gives more accurate defect localization than an LIT amplitude image or OBIRCH to determine the next FA steps.