Getting accurate fault isolation during failure analysis is mandatory for success of Physical Failure Analysis (PFA) in critical applications. Unfortunately, achieving such accuracy is becoming more and more difficult with today’s diagnosis tools and actual process node such as BCD9 and FinFET 7 nm, compromising the success of subsequent PFA done on defective SoCs. Electrical simulation is used to reproduce emission microscopy, in our previous work and, in this paper, we demonstrate the possibility of using fault simulation tools with the results of electrical test and fault isolation techniques to provide diagnosis with accurate candidates for physical analysis. The experimental results of the presented flow, from several cases of application, show the validity of this approach.

A typical workflow for advanced package failure analysis usually focuses around two key sequential steps: defect localization and defect characterization. Defect localization can be achieved using a number of complementary techniques, but electro optical terahertz pulse reflectometry (EOTPR) has emerged as a powerful solution. This paper shows how the EOTPR approach can be extended to provide solutions for the growing complexity of advanced packages. First, it demonstrates how localization of defects can be performed in traces without an external connection, through the use of an innovative cross-sectional probing with EOTPR. Then, the paper shows that EOTPR simulation can be used to extract the interface resistance, granting an alternative way of quantitative defect characterization using EOTPR without the destructive physical analysis. These novel approaches showed the great potential of EOTPR in failure analysis and reliability analysis of advanced packaging.

This paper explains how the authors used nanoprobing techniques and electrical characterization to trace a die failure to a problem with the photoresist used to mask the wafer for ion implantation. Nanoprobing and leakage current measurements revealed significant differences between the inner and outer fingers of a multi-finger native transistor. Based on simulations, the differences can be attributed to severe scattering at the active edge of the Pwell due to problems with the photoresist, resulting in nonuniform doping profiles and die failure.

Microstructure and its effect on mechanical behavior of ultrafine interconnects have been studied in this paper using a modeling approach. The microstructure from the processes of solidification, spinodal decomposition, and grain growth in ultrafine interconnects has highlighted its importance. The size, geometry and composition of interconnects as well as the elastic energy can influence microstructure and thus the mechanical behavior. Quantification of microstructure in ultrafine interconnects is a necessary step to establish the linkage between microstructure and reliability.

Analog simulation combined with Time Resolved Light Emission (TRE) can be used to evaluate different fault possibilities and to isolate the most likely fault candidate. In this paper we will describe an improved fault model derived from parasitic layout extraction.

The IC industry continues to find ways to improve the ability to correlate the electrical failure signature of devices with the physical failure location using different techniques. The purpose of this work is to show that improved transmission line pulse (TLP) testing technique of ESD (ElectroStatic Discharge) protection structures can provide accurate identification of leakage current to better identify where ESD stress testing should stop and failure analysis should begin. Besides the traditional current and voltage measurements at the Device Under Test (DUT), this new TLP testing technique includes the ability to correct for the measurement system losses for improved accuracy. The pulse width of the TLP is chosen to provide the same current amplitude damage level (electrical) as is found in the Human Body Model (HBM) ESD stress testing. This allows a one to one correlation between the two methods and hence the means to correlate the electrical damage of the device and the physical location of the failure site. An SCR (Silicon Controlled Rectifier) device is used as an example.

Electrical shorting in micro-electro-mechanical systems (MEMS) is a significant production and manufacturing concern. We present a new approach to localizing shorted MEMS devices using Thermally-Induced Voltage Alteration (TIVA) [1]. In TIVA, the shorted, thermally isolated MEMS device is very sensitive to thermal stimulus. The site of the MEMS short will respond as a thermocouple when heated. By monitoring the potential across the shorted MEMS device as a laser scans across the sample, an image showing the location of the thermocouple (short site) can be generated. The TIVA signal for thermally isolated MEMS devices is much higher than that observed for conventional IC interconnections. This results from the larger temperature gradients generated during laser scanning due to little or no substrate heat sinking. The capability to quickly localize shorted MEMS structures is demonstrated by several examples. Thermal modeling of heat distributions is presented and is consistent with the experimental results.

In IDDQ testing of CMOS ASICs (as in conventional voltage based testing) actual defect coverage, rather than modeled fault coverage figures are relevant to achieving product Q&R targets. This paper reports experimental data on the defect coverage of IDDQ vectors taken from several ASICs from different semiconductor suppliers. We present our generic IDDQ methodology that has been run on these ASICs, including automated IDDQ vector generation/grading and the high speed IDDQ monitor OCIMU. Data are presented on absolute IDDO defect coverage, as estimated from correlation with voltage based tests, on the relative defect coverage of pseudo-stuck-at and the toggle fault models, on the defect coverage of reduced IDDQ sets and on the pattern sensitivity Of IDDQ rejects. It is demonstrated that the pictures shown by modeled fault coverage and actual defect coverage can differ significantly and therefore, theoretical fault coverage figures are not the correct data to assure Q&R targets. We have measured very good IDDQ defect coverage on random logic, but we also show real life cases where IDDQ testing alone is inefficient in screening Q&R hazards.