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Contact resistance
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Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 447-453, October 28–November 1, 2024,
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High resistance failures in P+ and N+ contact chains were traced to contacts partially filled with silicon dioxide (SiO 2 ) instead of the intended tungsten. Investigation revealed that oxygen (O 2 ) entered the deposition chamber through a faulty valve during silane gas (SiH 4 ) flow for tungsten seed deposition. This contamination triggered a gas-phase reaction producing SiO 2 particles that partially filled the contacts. Analysis of reaction kinetics explained the predominance of SiO 2 formation over tungsten deposition: the bond dissociation energy for SiO 2 formation is lower than that for tungsten, and SiO 2 -producing molecular collisions occur more frequently than tungsten-producing ones. The issue was resolved by replacing the leaking valve.
Proceedings Papers
ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 396-398, November 13–17, 2011,
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Contact resistance from wafer acceptance test (WAT) data is one of the critical parameter to significantly affect fabrication process. While WAT data shows open/short fail, high resistance fail and leakage fail in contact chain structure, the first job in failure analysis (FA) field is to localize failure site. For example, High resistance failure and leakage failure sites can be localized by Infrared Ray Optical Beam Induced Resistance Change (IR-OBIRCH) detection. Most of open failure modes could be isolated by front side passive voltage contrast (PVC) technique. However, there is still a limitation to this technique while contacts are still connected to substrate in metal-1/contact/active chain structure. Active Voltage Contrast (AVC) [1, 2] is a good method to overcome this problem, but the major concern is how to mark the failure location in SEM based probing system. In this paper, we provide a novel backside passive voltage contrast method to improve the failure analysis technique. By thinning down silicon substrate to the active area, a new contact chain from active area is created. Therefore, novel backside PVC is applied to locate the failed site.
Proceedings Papers
ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 434-438, November 13–17, 2011,
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Using nanoprobing techniques to accomplish transistor parametric data has been reported as a method of failure analysis in nanometer scale defect. In this paper, we focus on how to identify the influence of Contact high resistance on device soft failures using nanoprobing analysis, and showing that the equivalent mathematical models could be used to describe the corresponding electrical data in a device with Contact high resistance issue. A case study was presented to verify that Contact volcano defect caused Contact high resistance issue, and this issue can be identified via physical failure analysis (PFA) method (e.g. Transmission Electron Microscope and Focus Ion Beam techniques) and nanoprobing analysis method. Finally, we would explain the physical root cause of Contact volcano issue.
Proceedings Papers
ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 446-452, November 13–17, 2011,
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The International Symposium for Testing and Failure Analysis (ISTFA) 2010 event added a focus topic on Counterfeiting in Electronics. This topic was chosen because of the emergence of this concern and the critical role that Failure Analysis plays in this challenge. Failure Analysts will be involved deeply as companies worldwide are attempting to reduce the impact of increasing numbers of counterfeit products in the supply line and in fielded products. This paper will attempt to provide an overview of the topic and support the contributors to ISTFA 2010 while providing additional resources for information.
Proceedings Papers
ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 54-57, November 14–18, 2010,
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High contact resistance can be caused by moisture absorption in low phosphorus content BPTEOS. Moisture diffused through the TiN glue layer is absorbed by the BPTEOS during subsequent thermal processes resulting in increased contact resistance. This failure mode was studied by combining different failure analysis methods and was confirmed by duplication on experimental wafers.
Proceedings Papers
ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 133-140, November 2–6, 2008,
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We present an analysis of tungsten vias fabricated by a focused ion beam with regard to the understanding of circuit editing strategies. The growth rate of W is ~10 times faster in high aspect ratio vias than on flat surfaces, and W in vias has 4 at. % more C but only one-tenth the Ga of surface-deposited W. We propose that vias act like small Faraday cups, trapping the energy of the Ga+ ions and the reaction byproducts to enhance the growth rate of W and to increase the C to W ratio in vias compared to flat surfaces. The resistivity of W in the vias determined by a least squares fit to resistance data is 250μΩ-cm, unchanged from the resistivity of W deposited on a flat surface. The resistances of the vias fabricated in a SiO2 layer to contact an underlying Al sheet layer fit well to either of two models: 1) an effective area model that invokes resistive via sidewalls that do not participate in conduction, and 2) an contact resistance model that invokes tapered vias with a constricted W/Al contact area.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 497-502, November 12–16, 2006,
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To reconstruct discrete device threshold characteristics at tungsten contact level with atomic force probe (AFP), specific care in making drive current measurements is essential. Kelvin probing as well as the proper placement of the AFP probes themselves is an absolute requirement for insuring precise measurements. For this paper, NFET and PFET test structures employing 3 micrometer gate widths are used to simulate a sense-amp device. The results obtained using normal pad-level probing on a conventional probe station with results from an AFP nanoprober with and without Kelvin sensing are compared. These measurements are also compared with the nominal or expected design rule values. Experimental results comparing AFP Kelvin measurements at contact level on the same MOSFET test structure versus measurement obtained conventionally at pad level underscores the importance and value of AFP Kelvin measurements.
Proceedings Papers
ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 311-315, November 6–10, 2005,
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Accurately measuring parameter mismatch for analog MOSFETs, such as the threshold voltage (Vt) or W/L ratio, is often required in analog circuit failure analysis. The challenge in probing analog MOSFETs using atomic force probing (AFP) is contact resistance. Contact resistance between AFP tips and tungsten contacts can cause large error at high current. This paper discusses measurement error caused by contact resistance and the techniques to identify and reduce the contact resistance effect.
Proceedings Papers
ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 58-66, November 14–18, 2004,
Abstract
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The power supply transient/quiescent signal (IDDT/IDDQ) methods that we propose for defect localization analyze regional signal variations introduced by defects at a set of power supply ports on the chip under test (CUT). The methods are based on the comparison of the CUT with a golden reference chip, either simulated or determined to be defect-free, with the objective of distinguishing anomalous signal behavior introduced by a defect from that introduced by process variations. However, variations in contact resistance between the probe card and the CUT introduces anomalies in the measured power supply signals that complicates the task of comparing data between chips. This paper presents hardware results that demonstrate the effectiveness of a previously developed calibration technique designed to eliminate these types of signal anomalies introduced by the testing environment. The CUT hardware data presented in this work is calibrated using simulations of the CUT’s power grid and special on-chip sources of stimuli called ‘calibration circuits’. Several novel Look-Up Table based defect localization techniques are proposed that analyze the calibrated power supplies signals. The results of predicting the locations of emulated defects in nine copies of a test chip demonstrate the effectiveness of the techniques.
Proceedings Papers
ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 157-161, November 14–18, 2004,
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Process options of FIB circuit edit accessing active area in silicon through chip backside are presented. The full process is divided in modules. The technological readiness of the different modules is discussed. New results for the two most critical modules, endpoint detection of the global FIB trench in silicon, and contact resistivity of FIB deposited metal interconnect on diffusion, are presented. Investigated endpoint detection processes are FIB image contrast of the wells and of STI (shallow trench isolation). The contact to diffusion is in the range of 2-5 x 10-7 Ωcm2 on highly doped n-Si, about 10x higher on highly doped p-Si, with linear I-V characteristic.
Proceedings Papers
ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 236-243, November 14–18, 2004,
Abstract
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Interaction of inline SEM inspections with tungsten window-1 integrity were investigated. Multiple SEMs were utilized and various points in the processing were inspected. It was found that in certain circumstances inline SEM inspection induced increased window-1 contact resistance in both source/drain and gate contacts, up to and including electrical opens for the source/drain contacts.
Proceedings Papers
ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 125-130, November 2–6, 2003,
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This paper correlates the reseat failure rates of a PCI option card to the use of thin gold plating across the contact fingers. This failure mechanism results in increased contact resistance and is often misdiagnosed due to its intermittent failure mode. As many new manufactures appear in Asia, the push for global competitiveness to achieve high volume and reduced costs can result in insufficient plating finishes being applied to the contact fingers. Compounding this problem is the fact the many companies use multiple raw board suppliers to meet these volume requirements. Many times the end user of the option card is unaware of the wide variation in contact plating thickness that may be present from one raw board source to another. Intermittent failures are one of the most common defects experienced in high volume assembly. Unless properly diagnosed, these failures can be attributed to finger debris, rework flux, solder paste contamination and even connector related issues. The typical fix, whether approved by the process or not, is for the manufacturing assembler to reseat all of the option cards and memory into the Motherboard connector sockets. Unless the proper troubleshooting approach is followed, isolating the true root cause of the actual failure can be missed. The difficulty in identifying the reseat problem is compounded by the fact that the failures are often intermittent in nature. While reseating may temporarily achieve sufficient mating between the board’s contact fingers and the connector contacts, it provides no long term fix. These unnecessary reseats also reduce the long-term durability of already thin plating affecting customer satisfaction and warranty costs. In the paper, we will expand on the theory behind the XRF plating thickness testing, including: • System theory • Test calibration • Part orientation • Test measurement criteria Additional analysis of metallurgical cross-sectioning was performed to correlate the XRF test readings to the actual plated layers. The measurements were completed by use of a SEM (Scanning Electron Microscopy).
Proceedings Papers
ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 305-310, November 2–6, 2003,
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The continued application and extension of Moore’s is Law driving semiconductor development into the deep submicron range. 90nm processes are pushing the limits of current technology, and announcements for 65nm and even smaller process developments are common place. Inspection and deprocessing tools are pacing these developments with moderate levels of success [1]. Fault isolation, however, and particularly physical fault isolation at these levels represents perhaps the most daunting of challenges facing today’s semiconductor companies. Possibly the most important failure analysis step, physical fault isolation of sub-micron devices, is growing increasingly more challenging. Traditional probe stations find limitation below 500nm feature sizes. Recent approaches to probing smaller geometries, such as AFM (Atomic Force Microscopy), have come up short in flexibility and applicability. Deposition of FIB pads can change circuit characteristics, is costly and time consuming, and is becoming increasingly more difficult as proximities decrease. Successful probing of structures smaller than 300nm require careful consideration to reduce and stabilize contact resistance (RC). A NANO-100TM probe station with SEM optics was used to analyze characteristics of, and the process needed to obtain stable, low RC for physical submicron fault isolation. Main discussion topics include probe tip oxidation, test timing and sample preparation. Probe tip selection, probe scrub, and attack angle are also mentioned. Recommendations and findings are presented for immediate application. It is shown that if the proper steps and considerations are made, stable RC of less than 10V is possible when probing sub-micron devices.
Proceedings Papers
Mechanical and Electrical Characterization of an IC Bond Pad Stack Using a Novel In-Situ Methodology
ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 486-495, November 2–6, 2003,
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The semiconductor industry’s efforts to integrate dielectrics into Si devices has driven characterization efforts to address the challenges presented by adoption of this new class of materials. Abundant literature exists on the considerations required for CMP process recommendations for successful fabrication, adhesion requirements for both fabrication and assembly, and considerations for interconnect structure to enable wire-bonding. There is also interest in understanding the wafer level test challenges presented by the low-K devices. In addition to the typical concerns about reaching the best compromise of good contact resistance (CRES) performance with a minimum amount of probe damage, low-K materials present an increased risk of compromising the dielectric or barrier layers beneath bond pads. For a better understanding of the dynamic contact phenomenon of probing and its effect on the integrated circuit (IC) metal stack, a specialized in-situ nanomanipulator tool was developed for simultaneous visualization of probing events with data recording of electrical and load measurements. This paper describes initial research with this new tool.
Proceedings Papers
ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 183-188, November 3–7, 2002,
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Focused Ion Beam (FIB) has been widely accepted in circuit modification and debugging of new chips and process technologies [1]. It has the advantages of rapid confirmation of design fixes and reducing the cost and time to build new masks. In this paper, we will describe the latest application of FIB to debugging Static Random Access Memory (SRAM) test chips processed on a dense copper metallization technology. Examples of finding leaky capacitors will be given. Individual transistors in the cell array have also been “fibbed” and characterization curves were measured. We compare the measurement with the SPICE simulation and discuss possible damage to the underlying transistors during FIB pad creation. Resistors in the periphery circuit were fibbed and measured with two and four point probes. Contact resistance was characterized and compared to that of Al interconnects. Example of finding problem vias with the help of cross-section and voltage contrast is given.
Proceedings Papers
ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 245-249, November 3–7, 2002,
Abstract
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Locating the defect site in current devices is complicated by their density and size. Voltage contrast (VC) imaging and backscattered electron (BSE) imaging are non-destructive beam-based location techniques. We can locate the defect to single poly line, contact and via by combining EMMI, LC, layout and bit map address information. Some reliability failure analysis cases are presented to demonstrate the effectiveness of the beam-based techniques. VC imaging and BSE imaging are used to locate the defect site precisely. The subsequent steps include deprocess and precision FIB cut for sample preparation. SEM or TEM is then used to identify failures caused by gate oxide pinhole, contact junction leakage, high butted contact resistance or tungsten residue.
Proceedings Papers
ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 403-407, November 3–7, 2002,
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Modifications directly to a transistor’s source/drain and polysilicon gate through the backside of a SOI device were made. Contact resistance data was obtained by creating contacts through the buried oxide layer of a manufactured test structure. A ring oscillator circuit was modified and the shift in oscillator frequency was measured. Finally, cross section images of the FIB created contacts were presented in the paper to illustrate the entire process.
Proceedings Papers
ISTFA1999, ISTFA 1999: Conference Proceedings from the 25th International Symposium for Testing and Failure Analysis, 161-169, November 14–18, 1999,
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Electrical data from chromium-silicon-carbon (CrSiC) thin film resistors (tfr) consistently showed highly variable contact resistance (Rc) to the aluminum (Al) interconnect. Transmission electron microscopy data from CrSiC/Al interfaces exhibiting high Rc showed a conformal, amorphous layer sandwiched between the tfr and Al. Auger data from the tfr/Al interface showed this ‘crud’ layer to contain increased C, S, and SiOx. Auger data from CrSiC films on test wafers exposed to the process steps before Al deposition showed additional growth of the ‘crud’ layer after each photoresist (PR) operation. In addition, Rc variability was reduced on product wafers from split lots when 2x the normal PR strip time was used compared to the normal strip time. A Designed Experiment (DOE) to examine improving the removal of this ‘crud’ layer was run on product lots utilizing two factors: the standard strip and a two-step strip. Electrical results for both Rc and die yield were significantly improved using the two-step process. The variability of the Rc was also reduced.
Proceedings Papers
ISTFA1996, ISTFA 1996: Conference Proceedings from the 22nd International Symposium for Testing and Failure Analysis, 149-158, November 18–22, 1996,
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We present the results of recent failure analysis of an advanced, 0.5 um, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.