This paper presents a number of case studies in which various methods and tools are used to localize resistive open defects, including two-terminal IV, two-terminal electron-beam absorbed current (EBAC), electron beam induced resistance change (EBIRCH), pulsed IV, capacitance-voltage (CV) measurements, and scanning capacitance microscopy (SCM). It also reviews the advantages and limitations of each technique.

This paper demonstrates a novel defect localization approach based on EBIRCH isolation conducted from the backside of flip chips. It discusses sample preparation and probing considerations and presents a case study that shows how the technique makes it possible to determine the root cause of subtle defects, such as bridging, in flip chip failures.

An experimental study was undertaken to determine the minimum level of leakage or shorting current that could be detected by electron-beam induced resistance change (EBIRCH) analysis. A 22-nm SRAM array was overstressed with a series of gradually increasing voltage biases followed by EBIRCH scans at 1 V and 2-kV SEM imaging until fins were observed. It was found that the fins of a pulldown device could be imaged by EBIRCH at just 12 nA of shorting current, representative of a soft failure. Stressing the sample at higher voltages eventually created an ohmic short, which upon further investigation, strongly suggested that the Seebeck effect plays a significant role in EBIRCH analysis.

In this paper, we describe the difference between oscilloscope pulsing tests and waveform generator fast measurement unit (WGFMU) tests in analyzing high-resistance defects in DRAM main cells. Nanoprobe systems have various constraints in terms of pulsing whether it involves an oscilloscope or pulse generator. There are certain types of devices, such as DRAM cells, for which these systems are ineffective because saturation currents are too small. In this paper, we address this constraint and propose a new way to conduct pulsing tests using the WGFMU's arbitrary linear waveform generator in combination with an electro-optical nanoprobe.

Many semiconductor products are manufactured with mature technologies involving the uses of aluminum (Al) lines and tungsten (W) vias. High resistances of the vias were sometimes observed only after electrical or thermal stress. A layer of Ti oxide was found on such a via. In the wafer processing, the post W chemical mechanical planarization (WCMP) cleaning left residual W oxide on the W plugs. Ti from the overlaying metal line spontaneously reduced the W oxide, through which Ti oxide formed. Compared with W oxide, the Ti oxide has a larger formation enthalpy, and the valence electrons of Ti are more tightly bound to the O ion cores. As a result, the Ti oxide is more resistive than the W oxide. Consequently, the die functioned well in the first test in the fab, but the via resistance increased significantly after a thermal stress, which led to device failure in the second test. The NH4OH concentration was therefore increased to more effectively remove residual W oxide, which solved the problem. The thermal stress had prevented the latent issue from becoming a more costly field failure.

Since the early beginning of the integrated circuits, electromigration is a reliability issue of first interest. In 3-dimensional structures, electromigration is responsible for the formation of voids in lines connected to the Through Silicon Via (TSV). To our knowledge, this paper presents the first in operando electromigration experiment in a Scanning Electron Microscope (SEM) performed for 3D integration. The experimental protocol, including sample preparation and temperature regulation, is detailed. A current of 25 mA is injected in a structure heated at 350 °C for about 900 h. The evolution of voids is monitored and explained. Void growth occurs step by step, so that the microstructure may be assumed to play a major role in the depletion mechanism. The behavior of the electrical resistance is analyzed using the SEM micrographs.

With the scaling down of semiconductor devices to nanometer range, fault isolation and physical failure analysis (PFA) have become more challenging. In this paper, different types of fault isolation techniques to identify gross short failures in nanoscale devices are discussed. The proposed cut/deprocess and microprobe/bench technique is an economical and simple way of identifying low resistance gross short failures.

The electrical resistance Cu film on flexible substrate was investigated in cyclic bending deformation. The electrical resistance of 1 µm thick Cu film on flexible substrate increased up to 120 % after 500,000 cycles in 1.1 % tensile bending strain. Crack and extrusion were observed due to the fatigue damage of metal film. Low bending strain did not cause any damage on metal film but higher bending strain resulted in severe electrical and mechanical damage. Thinner film showed higher fatigue resistance because of the better mechanical property of thin film. Cu film with NiCr under-layer showed poorer fatigue resistance in tensile bending mode. Ni capping layer did not improve the fatigue resistance of Cu film, but Al capping layer suppressed crack formation and lowered electrical resistance change. The NiCr under layer, Ni capping layer, and Al capping layer effect on electrical resistance change of Cu film was compared with Cu only sample.

Contact resistance from wafer acceptance test (WAT) data is one of the critical parameter to significantly affect fabrication process. While WAT data shows open/short fail, high resistance fail and leakage fail in contact chain structure, the first job in failure analysis (FA) field is to localize failure site. For example, High resistance failure and leakage failure sites can be localized by Infrared Ray Optical Beam Induced Resistance Change (IR-OBIRCH) detection. Most of open failure modes could be isolated by front side passive voltage contrast (PVC) technique. However, there is still a limitation to this technique while contacts are still connected to substrate in metal-1/contact/active chain structure. Active Voltage Contrast (AVC) [1, 2] is a good method to overcome this problem, but the major concern is how to mark the failure location in SEM based probing system. In this paper, we provide a novel backside passive voltage contrast method to improve the failure analysis technique. By thinning down silicon substrate to the active area, a new contact chain from active area is created. Therefore, novel backside PVC is applied to locate the failed site.

Using nanoprobing techniques to accomplish transistor parametric data has been reported as a method of failure analysis in nanometer scale defect. In this paper, we focus on how to identify the influence of Contact high resistance on device soft failures using nanoprobing analysis, and showing that the equivalent mathematical models could be used to describe the corresponding electrical data in a device with Contact high resistance issue. A case study was presented to verify that Contact volcano defect caused Contact high resistance issue, and this issue can be identified via physical failure analysis (PFA) method (e.g. Transmission Electron Microscope and Focus Ion Beam techniques) and nanoprobing analysis method. Finally, we would explain the physical root cause of Contact volcano issue.

We have demonstrated the sample fabrication by focused ion beam (FIB) milling and delineation etch gas which makes it possible to directly measure resistance in a cross section of semiconductor devices with a nano probe after cell fabrication. With direct evaluation of electrical properties, this technique can help improve semiconductor devices.

The International Symposium for Testing and Failure Analysis (ISTFA) 2010 event added a focus topic on Counterfeiting in Electronics. This topic was chosen because of the emergence of this concern and the critical role that Failure Analysis plays in this challenge. Failure Analysts will be involved deeply as companies worldwide are attempting to reduce the impact of increasing numbers of counterfeit products in the supply line and in fielded products. This paper will attempt to provide an overview of the topic and support the contributors to ISTFA 2010 while providing additional resources for information.

High contact resistance can be caused by moisture absorption in low phosphorus content BPTEOS. Moisture diffused through the TiN glue layer is absorbed by the BPTEOS during subsequent thermal processes resulting in increased contact resistance. This failure mode was studied by combining different failure analysis methods and was confirmed by duplication on experimental wafers.

One issue that faces failure analysis at the system level is impedance mismatched transmission lines resulting from developers pushing the edge of trace layout recommendations. When transmission lines on printed circuit boards are routed in such a way as to allow for impedance mismatches, the effects can be unwanted on the signal that the line carries. Techniques can be used for discovering if capacitance, resistance, or split planes are creating the impedance mismatches that are resulting in the system level failure seen by the customer.

Electrical Test (ET) structures are used to monitor the health and yield of a process line. With the scaling down of semiconductor devices to nanometer ranges, the number of metal lines and vias increase. In order to simulate the electrical performance of devices and to increase the sensitivity for line health check, ET structures are designed to be more complicated with a larger area. Hence, fault isolation and failure analysis become more challenging. In this paper, the combined technique of Scanning Electron Microscope (SEM) Passive Voltage Contrast (PVC), Nanoprobing technique, and Divide and Conquer Method (DCM) are proposed to locate open failure and high resistance failure in an ET via chain.

Electrical resistance of M1/M3 stack for Aluminium based technology showed anomalous values when no Ti is inserted between AlCu and cap TiN. Process investigations lead to suspect formation of AlN layer at this interface. Blanket wafers were processed at different temperatures to reproduce the layer formation and characterize the film by numerous techniques including XPS and EELS-TEM profiling. Full use of the different results shows the formation of a very thin (a few nms) and highly resistive AlN layer at the cap TiN / AlCu interface as well as a thicker but less resistive AlN layer at the bottom TiN / AlCu interface. PVD process changes were attempted to reduce the M1/M3 button stack resistance. Modification of the N2/Ar flow ratio for TiN sputtering shows slightly more stoechiometric TiN with reduced stack resistance by 35%.

Advanced technologies with higher gate leakage due to oxide tunneling current enable detection of high resistance faults to gate nodes using a straight forward resistance measurement.

This paper presents a case study on via high resistance issue. A logical failure analysis process EDCA ( E ffect, D efect, C ause, and A ction) is successfully applied to find out the failure mechanism, pinpoint the root cause and solve the problem. It sets up a very good example of how to do tough failure analysis in a controllable way.

We present an analysis of tungsten vias fabricated by a focused ion beam with regard to the understanding of circuit editing strategies. The growth rate of W is ~10 times faster in high aspect ratio vias than on flat surfaces, and W in vias has 4 at. % more C but only one-tenth the Ga of surface-deposited W. We propose that vias act like small Faraday cups, trapping the energy of the Ga+ ions and the reaction byproducts to enhance the growth rate of W and to increase the C to W ratio in vias compared to flat surfaces. The resistivity of W in the vias determined by a least squares fit to resistance data is 250μΩ-cm, unchanged from the resistivity of W deposited on a flat surface. The resistances of the vias fabricated in a SiO2 layer to contact an underlying Al sheet layer fit well to either of two models: 1) an effective area model that invokes resistive via sidewalls that do not participate in conduction, and 2) an contact resistance model that invokes tapered vias with a constricted W/Al contact area.

A failure incurred in the front-end is typically a bottleneck to production due the need for physical failure analysis (PFA). Often the challenge is to perform timely localization of the front-end defect, or finding the exact physical defect for process improvement. Many process parameters affect the device behaviour and cause the front-end defect. Simply, the failures are of two types: high-resistance and leakage. A leakage mode defect is the most difficult to inspect. Although conductive atomic force microscopy and six probes nano-probing are popular tools for front-end failure inspection, some specific defects still need more effort. The electrical phenomenon and analysis of a crystalline defect will be demonstrated in this paper. The details will be discussed below.