We propose an unbiased electrical fault isolation methodology for locating gate oxide breakdown failures in MOSFETs. The test vehicle involves a sub-15nm technology DRAM device which failed due to time-dependent dielectric breakdown (TDDB). This methodology introduces an implementation of Optical Beam Induced Resistance Change with no applied external bias (zero input voltage). From OBIRCH analysis, a change in current was achieved near failure site. This principle was explained based on Seebeck effect and equivalent circuit modeling of the MOSFET drain within Seebeck generator. A physical cross section using the Focused Ion Beam (FIB) revealed a gate oxide breakdown along the location of the OBIRCH spot, illustrating the benefit of an unbiased fault isolation to preserve the failure mechanism. This study proves that gate oxide breakdown site can still be located even with no external voltage applied, preserving the device condition of nanoscale DRAM, and eliminating the chances of altering the failure mechanism as a result of the applied external voltage stress.

Gate oxide breakdown has always been a critical reliability issue in Complementary Metal-Oxide-Silicon (CMOS) devices. Pinhole analysis is one of the commonly use failure analysis (FA) technique to analysis Gate oxide breakdown issue. However, in order to have a better understanding of the root cause and mechanism, a defect physically without any damaged or chemical attacked is required by the customer and process/module departments. In other words, it is crucial to have Transmission Electron Microscopy (TEM) analysis at the exact Gate oxide breakdown point. This is because TEM analysis provides details of physical evidence and insights to the root cause of the gate oxide failures. It is challenging to locate the site for TEM analysis in cases when poly gate layout is of a complex structure rather than a single line. In this paper, we developed and demonstrated the use of cross-sectional Scanning Electron Microscope (XSEM) passive voltage contrast (PVC) to isolate the defective leaky Polysilicon (PC) Gate and subsequently prepared TEM lamella in a perpendicular direction from the post-XSEM PVC sample. This technique provides an alternative approach to identify defective leaky polysilicon Gate for subsequent TEM analysis.

We report and demonstrate a new methodology for the localization of dielectric breakdown sites in through-silicon via (TSV) structures. We apply a combination of optical beam induced resistance change (OBIRCH) and mechanical/chemical chip deprocessing techniques to localize nm-sized pinhole breakdown sites in a high aspect ratio 3x50 ìm TSV array. Thanks to the wavelength-selective absorption process in silicon, we can extract valuable defect depth localization info from our laser stimulation measurement. After chip deprocessing we inspect and localize the defect site in the dielectric liner using a scanning electron microscope (SEM). We confirm our results and analysis by cross-sectioning a TSV with a focused-ion beam (FIB).

This paper describes the detailed process of failure analysis (FA) of a 16-bit transceiver. The FA included six steps: electronic parametric testing, visual inspection, optical beam induced resistance change to isolate failure location, SEM inspection of the breakdown, electro static discharge (ESD) root identification, and ESD test to prove the identification. FA showed that the short circuit was the result of a breakdown between the I/O resistor and the substrate, and the cause of the breakdown was most likely an ESD event. In a series of electrical over stress/ESD tests performed, the field failure signature was replicated with a MM ESD model, thereby identifying the root cause of the ESD failure.

A novel approach for the localization of weak points in thin transistor and capacitor oxides before electrical breakdown will be presented in this paper. The proposed approach utilizes Electron Beam Absorbed Current (EBAC) imaging based on Scanning Electron Microscopy (SEM). This technique uses the generation of additional charge carriers within the semiconductor substrate level by scanning with a focused electron beam. Over a thin transistor or capacitor oxide layer inside the interaction volume of the electron beam an increased tunnel current is visualized by EBAC and shows areas with different current intensities indicating weak points. These soft defect areas are investigated in comparison to references which were analyzed by using cross sectioning in a dual beam FIB/SEM system followed by a high resolution Transmission Electron Microscopy (TEM) investigation. The feasibility of this new technique is demonstrated on a defective transistor gate oxide test structure.

For 22nm and below technologies which involve as many as fifteen back end of the line (BEOL) metallization levels, these leading edge technology nodes pose real challenges in defect localization and root cause analysis. Due to scaling, the reduction in copper land cross section area is accompanied by increased current density and electromigration failure rates. Time to Dielectric Defect Breakdown (TDDB) shows an increase in fallout with successive technology node from 32nm and below. Similarly, the reduced dielectric thickness increases the electric field stress prompting the necessity for porous, ultra low k dielectric (ULK) films. Defect localization is difficult due to the complexity of these multiple metal layers along with the presence of the porous, low k dielectric films which exhibit shrinkage or void formation when exposed to an e-beam/FIB ion beam > 1keV. Due to the porosity of these ULK dielectric films, they are especially susceptible to gallium ion implantation. It has been reported elsewhere that suppressing copper diffusion at the copper land/cap interface can be achieved by depositing a thin layer of CoWP and doping the copper seed layer with manganese [15, 16, 17]. However, a method for analytically confirming that these approaches for suppressing the copper diffusion do not affect TDDB performance/electromigration behavior must be demonstrated.

In this paper a novel approach for precise localisation of thin oxide breakdowns in transistor or capacitor structures by electron beam absorbed current (EBAC) imaging based on Scanning Electron Microscopy will be presented. The technique significantly improves sensitivity and lateral resolution of short localisation in comparison to standard techniques, e.g. Photoemission Microscopy, and provides direct defect navigation within a combined FIB/SEM system for further cross section analysis. The oxide short is minimal affected by electrical stimulation preserving its original defect structure for further physical root cause analysis. The feasibility of this new technique is demonstrated on a gate oxide (GOX) and two capacitor oxide (COX) breakdown failures.

In this paper, we propose a new methodology and test system to enable the early detection and precise localization of Time-Dependent-Dielectric-Breakdown (TDDB) occurrence in Back-End-of-Line (BEOL) interconnection. The methodology is implemented as a novel Integrated Reliability Test System (IRTS). In particular, through our methodology and test system, we can easily synchronize electrical measurements and emission microscopy images to gather more accurate information and thereby gain insight into the nature of the defects and their relationship to chip manufacturing steps and materials, so that we can ultimately better engineer these steps for higher reliable systems. The details of our IRTS will be presented along with a case study and preliminary analysis results.

In this paper, a zero yield case relating to a systematic defect in N+ poly/N-well varactor (voltage controlled capacitor) on the RF analog circuitry will be studied. The systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP current Imaging and nano-probing, manual layout path tracing, FIB circuit edit, selective etching together with Fab investigation is used to understand the root cause as well as failure mechanism proposed. This process is particularly critical for a foundry company with restricted access to data on test condition setup to duplicate the exact failure as well as no layout tracing available at time of analysis. The systematic defect was due to gate oxide breakdown as a result of implanter charging. It serves as a good reference to other wafer Fabs encountering such an issue.

Fundamental consideration for CDM (Charged Device Model) breakdown was investigated with 90nm technology products and others. According to the result of failure analysis, it was found that gate oxide breakdown was critical failure mode for CDM test. High speed triggered protection device such as ggNMOS and SCR (Thyristor) is effective method to improve its CDM breakdown voltage and an improvement for evaluated products were confirmed. Technological progress which is consisted of down-scaling of protection device size and huge number of IC pins of high function package makes technology vulnerable and causes significant CDM stress. Therefore, it is expected that CDM protection designing tends to become quite difficult. In order to solve these problems in the product, fundamental evaluations were performed. Those are a measurement of discharge parameter and stress time dependence of CDM breakdown voltage. Peak intensity and rise time of discharge current as critical parameters are well correlated their package capacitance. Increasing stress time causes breakdown voltage decreasing. This mechanism is similar to that of TDDB for gate oxide breakdown. Results from experiences and considerations for future CDM reliable designing are explained in this report.

This paper analyzes several SRAM failures using nano-probing technique. Three SRAM single bit failures with different kinds of Gox breakdown defects analyzed are gross function single bit failure, data retention single bit failure, and special data retention single bit failure. The electrical characteristics of discrete 6T-SRAM cells with soft breakdown are discussed and correlated to evidences obtained from physical analysis. The paper also verifies many previously published simulation data. It utilizes a 6T-SRAM vehicle consisting of a large number of SRAM cells fabricated by deep sub-micron, dual gate, and copper metallization processes. The data obtained from this paper indicates that Gox breakdown location within NMOS pull-down device has larger a impact on SRAM stability than magnitude of gate leakage current, which agrees with previously published simulation data.

The effect of ash chemistries, N2/H2 and H2, on time-dependent dielectric breakdown (TDDB) lifetime has been investigated for Cu damascene structure with a carbon-doped CVD ultra low-k (ULK, k=2.5) intermetal dielectric. Two failure modes, interfacial Cu-ion-migration and Cu diffusion through the bulk intermetal ULK were attributed to the TDDB degradation for the H2 ash.The interfacial Cu-ion-migration was the only dominated failure mode for the N2/H2 ash. The nitrogen species in the N2/H2 plasma proved to be capable of forming a nitrided protection layer on the surface of the ULK. This nitrided layer suppressed further plasma damage during the ash process and thus lessened the TDDB degradation by preventing Cu diffusion through the bulk ULK.

In modern integrated circuits (IC) using sub-micron or deep sub-micron process rules, substrate dislocation is a common failure mechanism in SRAM or embedded SRAM products. Depending on the position of substrate dislocation in the SRAM cell, it may result in problems including junction or contact leakage, gate oxide early breakdown, low threshold voltage, and poor data retention. In this paper, we’ll focus on the test methodology and physical failure analysis to dig out the failure mechanism, substrate dislocation under SRAM pass gate and node contact. In addition, we will measure the electrical behavior of such substrate dislocation. Several FA techniques, such as Passive Voltage Contrast (PVC) [1] pad deposition by Focus Ion Beam (FIB), and electrical micro probing [2] will be used during leakage verification and measurement.

Interaction of inline SEM inspections with tungsten window-1 integrity were investigated. Multiple SEMs were utilized and various points in the processing were inspected. It was found that in certain circumstances inline SEM inspection induced increased window-1 contact resistance in both source/drain and gate contacts, up to and including electrical opens for the source/drain contacts.

The presence of sharp, “pointed” features on Printed Circuit Board (PCB) power planes and their contribution to increased plane-to-plane electric fields is studied as a potential root cause for PCB level dielectric breakdown. The results of this study are used to gauge the propensity for heat generation due to current leakage through pre-preg. A first order approximation for the E-field between a power and ground plane is Ê = V/d (1) where Ê is the electric field, V is the potential across the planes, and d is the separation between the planes. While this first order approximation is correct for infinite parallel planes, simulations show that second and third order effects that exist on real boards can multiply the effective Ê by more than 100x. The second order effects are primarily dependent on the local sharpness of planar shapes, and plane-to-plane separation. This amplified Efield could potentially breakdown pre-preg locally and initiate current leakage. Leakage through prepreg can grow over time as a leakage path becomes established and can wreak havoc with power rails or create a local ohmic conduction path that can lead to board level failures. A test platform and a series of experiments were developed to understand and quantify the various parameters that contribute to these failures. Tests revealed that given an ambient temperature of 70C, the presence of pointed features in planes reduces the breakdown voltage by at least 75%. It is suspected that under the right conditions, a breakdown will occur on a sharp shape if given sufficient duration of exposure to even low voltages.

This paper describes a case study of a back end of the line low-k time dependent dielectric breakdown failure analysis. Due to the extremely large size of the stressed test structure, isolation of the defect and root cause determination can be quite difficult. In this particular study the defect was determined to lie in an approximately 100 um2 area and top down SEM inspection did not indicate any obvious defect. In an effort to further isolate the defect, an image comparison analysis was performed to highlight the differences between the fail area and an assumed good area of the test structure. A local area within the failing region was identified and imaged in cross section via TEM. The source of contamination which caused the fail was identified and appropriate process actions were implemented to remove the defect mechanism.

Backside photoemission microscopy [1-2] was used to analyze the major yield loss of a communication product fabricated with submicron CMOS process: functional failures of phase-lock-loop (PLL). The PLL block was covered by five metal layers and three of them were bulk metals. Based upon the backside photoemissions detected on the capacitor structures within the PLL block and the ruptures observed at the emission spots on the polysilicon and gate oxide or of the capacitor after physical deprocessing, the failure was proved due to the capacitor gate-oxide breakdown. This was believed to be caused by the plasma-induced-damage during high-density-plasma (HDP) CVD oxide deposition after the front-end processes, as only the lots from one HDP-CVD deposition equipment have very high percentage PLL functional failure. Subsequent machine commonality check did find non-uniform inter layer dielectric (ILD) thickness from this equipment, which indicated the non-uniform plasma intensity occurred during the ILD film deposition. This was further confirmed by the finding of a worn-out gas-shower-head in this system. The abnormal high density of plasma created extra charging and caused the PLL poly capacitor’s gate oxide breakdown due to the antenna effect. After replacing the gas showerhead, the failure disappeared and yield was back to normal. Through this low yield analysis, we demonstrated an effective application of backside photoemission microscopy to fab yield improvement.

Reliability of low standby current (Isb) CMOS circuits is impacted by extremely small non-fault resistive defects which, without compromising logic functionality or timing specifications, cause Isb currents well in excess of device specifications. A primary cause of high Isb, identified through failure analysis, is due to Crystal Originated Pits (COPs) defects, whereat thin oxide is more prone to electrical breakdown.

Due to the continuously decreasing cell size of DRAMs and concomitantly diminishing thickness of some insulating layers new failure mechanisms appear which until now had no significance for the cell function. For example high resistance leakage paths between closely spaced conductors can lead to retention problems. These are hard to detect by electrical characterization in a memory tester because the involved currents are in the range of pA. To analyze these failures we exploit the very sensitive passive voltage contrast of the Focused Ion Beam Microscope (FIB). The voltage contrast can further be enhanced by in-situ FIB preparations to obtain detailed information about the failure mechanism. The first part of this paper describes a method to detect a leakage path between a borderless contact on n-diffusion and an adjacent floating gate by passive voltage contrast achieved after FIB circuit modification. In the second part we will demonstrate the localization of a DRAM trench dielectric breakdown. In this case the FIB passive voltage contrast technique is not limited to the localization of the failing trench. We can also obtain the depth of the leakage path by selective insitu etching with XeF2 stopped immediately after a voltage contrast change.

The electrical and chemical properties of insulators produced by codeposition of siloxane compounds or TEOS with oxygen in a focused ion beam (FIB) system were investigated. Metal-insulator-metal capacitor structures were fabricated and tested. Specifically, leakage current and breakdown voltage were measured and used to calculate the effective resistance and breakdown field. Capacitance measurements were performed on a subset of the structures. It was found that the siloxanebased FIB-insulators had superior electrical properties to those based on TEOS. Microbeam Rutherford backscattering spectrometry analysis and Fourier transform infrared spectroscopy were used to characterize the films and to help understand the differences in electrical behavior as a function of gas chemistry and deposition conditions. Finally, a comparison is made between the results presented here, previous results for FIB-deposited insulators, and typical thermally-grown gate oxides and interlevel dielectric Si02 insulators.