Low voltage power MOSFETs often integrate voltage spike protection and gate oxide ESD protection. The basic concept of complete-static protection for the power MOSFETs is the prevention of static build-up where possible and the quick, reliable removal of existing charges. The power MOSFET gate is equivalent to a low voltage low leakage capacitor. The capacitor plates are formed primarily by the silicon gate and source metallization. The capacitor dielectric is the silicon oxide gate insulation. Smaller devices have less capacitance and require less charge per volt and are therefore more susceptible to ESD than larger MOSFETs. A FemtoFETTM is an ultra-small, low on-resistance MOSFET transistor for space-constrained handheld applications, such as smartphones and tablets. An ESD event, for example, between a fingertip and the communication-port connectors of a cell phone or tablet may cause permanent system damage. Through electrical characterization and global isolation by active photon emission, the authors identify and distinguish ESD failures. Thermographic analysis provided additional insight enabling further separation of ESD failmodes. This paper emphasizes the role of failure analysis in new product development from the create phase through to product ramp. Coupled with device electrical simulation, the analysis observations led to further design enhancement.

One issue that faces failure analysis at the system level is impedance mismatched transmission lines resulting from developers pushing the edge of trace layout recommendations. When transmission lines on printed circuit boards are routed in such a way as to allow for impedance mismatches, the effects can be unwanted on the signal that the line carries. Techniques can be used for discovering if capacitance, resistance, or split planes are creating the impedance mismatches that are resulting in the system level failure seen by the customer.

Series capacitors, under certain conditions, within high speed differential pair signals were found to have negative effects on mother board functions inside a personal computer (PC). It was noted in one case study that three conditions affected capacitors with this type of application: capacitor aging, DC offset voltage, and cold temperatures. These conditions led to the decrease in capacitance which then disabled the network connection inside the PC. It was concluded that a strategically chosen capacitor type alleviates these conditions. The capacitor type primarily depends on the dielectric material.

This paper presents the results of a study to assess the timing measurement capabilities of e-beam probes and how they compare to mechanical probes in terms of sampling time, accuracy, and repeatability. Analysis of the data indicates that the transient response of mechanical probes is prone to overshoot and ringing, which contributes significantly to measurement error and uncertainty. E-beam probes, on the other hand, are subject to charging effects and interference which, as the authors show, can be effectively eliminated, facilitating high-speed timing measurements accurate to within a few picoseconds.

The ESD Association standard ANSI/ESDA S-5.1 1993 for testing sensitivity to the Human Body Model (HBM) 1 forms the basis around which the majority of automated HBM ESD simulators have been constructed. As device pin counts increase it is unlikely that new larger simulators for > 512 pins will be capable of meeting this standard 2, since increased parasitics will increase the effective socket (stray) capacitance. However, such larger HBM simulators are expected to meet both the JEDEC Standard JESD-22-114A, 1997 3 and the newly issued ESDA Standard Test Method, ESD STM 5.1, 19984. This paper begins to evaluate the several questions regarding the correlation of HBM Withstand Voltage when used to characterize state-of-the-art semiconductor IC's, between simulators meeting the (NEW) standards JESD 22, ESD STM- 5.1 and those existing simulators presently in daily use, which typically meet the (OLD) ESDA S-5.1. This paper for the first time investigates the impact of "effective" socket capacitance in the same tester; i.e., with the same discharge model and the same pin selection mechanism. The experimental investigation was based on stressing three different sub-micron CMOS technology products; firstly on a simulator meeting the OLD standard and then on a modified version of this simulator meeting the NEW standards. Electrical properties of damaged pins and physical analysis was used to establish common Failure Signatures5 for the two mother boards.