We present a study of dislocation conductivity under forward bias in p-GaN/AlGaN/GaN heterojunctions on a GaN-on-Si substrate, which are part of every p-GaN HEMT structure. Conductive atomic force microscopy (C-AFM) is combined with structural analysis by scanning transmission electron microscopy (STEM) and defect selective etching (DSE). The density of conductive TDs was found to be 5 × 10 6 cm -2 , using semi-automatic measurements to gather larger statistics on a delayered HEMT sample. IV measurements show a shift in turn-on voltage at the leakage positions. To characterize the type of the conductive TDs, DSE with a KOH/NaOH melt was used. Three distinct etch pit sizes were observed after 5 s etch time, with large, medium and edge pits according to STEM characterization seemingly corresponding to screw, mixed and edge TDs, respectively. However, characterization by DSE etch pit size alone was found to be unreliable, as STEM TD typing of seven conductive TDs using two-beam diffraction conditions revealed mostly pure screw and mixed-type dislocations with medium-sized etch pits as origin of the observed leakage current. Our work highlights the limitations of DSE as a characterization method and recommends additional validation by STEM for each new material system, investigated layer, and etching setup. The implications of finding conductive TDs with screw-component under low forward bias conditions on device behavior and the limitations of the C-AFM method are discussed. Based on the results, it is not anticipated that the identified conductive TDs will have a substantial effect on a GaN HEMT device. Overall, this study provides important insights into the electrical properties of TDs and offers useful recommendations for future research in this area.

In this paper, the failure analysis of InGaAs/GaAs-on-Si nanoridge laser diodes using the electron beam based nano-probing technique is presented. These III-V laser devices are fabricated using the nano-ridge engineering approach where the misfit dislocations generated during the growth of InGaAs/GaAs layers on silicon substrate are confined away from the active region. It is observed that the applied electrical stress causes degradation of electrical properties of the laser devices. We demonstrate the application of the electron beam induced current (EBIC) technique for failure analysis of nano-ridge lasers. This high-resolution technique helps to visualize the local distribution of the electric field in a nano-ridge p-i-n diode. The EBIC signal from the reference (electrically unstressed) device and the electrically stressed device is compared and hence can be used to identify the defective region. Furthermore, in-situ electrical stress experiments are performed for systematic analysis of the impact of electrical stress on the EBIC results.

In nanoscience, techniques based on Atomic Force Microscope (AFM) stand as a cornerstone for exploring local electrical, electrochemical and magnetic properties of microelectronic devices at the nanoscale. As AFM's capabilities evolve, so do the challenges of data analysis. With the aim of developing a prediction model for AFM mappings, based on Machine Learning, this work presents a step towards the analysis and benefit of Big Data recorded in the hyperspectral modes: AFM DataCube. The MultiDAT-AFM solution is an advanced 2000-line Python-based tool designed to tackle the complexities of multi-dimensional measurements and analysis. MultiDAT-AFM offers visualization options, from acquired curves to scanned mappings, animated mappings as movies, and a real 3D-cube representation for the hyperspectral DataCube modes. In addition, MultiDAT-AFM incorporates a Machine Learning algorithm to predict mappings of local properties. After evaluating two supervised Machine Learning algorithms (out of the eight tested) for regression, the Random Forest Regressor model emerged as the best performer. With the refinement step, a root mean square error (RMSE) of 0.18, an R 2 value of 0.90 and an execution time of a few minutes were determined. Developed for all AFM DataCube modes, the strategy and demonstration of MultiDAT-AFM are outlined in this article for a silicon integrated microelectronic device dedicated to RF applications and analyzed by DataCube Scanning Spreading Resistance (DCUBE-SSRM).

Mechanical sample preparation is a crucial and indispensable step in modern failure analysis (FA). Traditional methods excel in reducing bulk silicon to thicknesses of several tens of micrometers. However, contemporary demands necessitate sample preparation below 10 µm or even below 5 µm, which is challenging, time-consuming, and requires an expensive toolset and advanced operator expertise. Existing methods, which rely on mechanical components for bulk removal, induce mechanical stress and microcracks that can alter the electrical characteristics of the sample. Maintaining the sample's electrical behavior is essential for accurate FA. This paper introduces a novel approach to sample preparation that employs concepts from wafer-level chemical mechanical polishing (CMP). This method ensures reliable sample preparation without introducing microcracks, accurately halts material removal at the shallow trench isolation (STI) – or deep STI - level, and maintains the sample's electrical functionality. The proposed approach is discussed in detail, including successful thinning of various sample types to the STI level, which were subsequently tested for electrical functionality.

High resistance failures in P+ and N+ contact chains were traced to contacts partially filled with silicon dioxide (SiO 2 ) instead of the intended tungsten. Investigation revealed that oxygen (O 2 ) entered the deposition chamber through a faulty valve during silane gas (SiH 4 ) flow for tungsten seed deposition. This contamination triggered a gas-phase reaction producing SiO 2 particles that partially filled the contacts. Analysis of reaction kinetics explained the predominance of SiO 2 formation over tungsten deposition: the bond dissociation energy for SiO 2 formation is lower than that for tungsten, and SiO 2 -producing molecular collisions occur more frequently than tungsten-producing ones. The issue was resolved by replacing the leaking valve.

As technology nodes continue to shrink, Scanning Electron Microscopy (SEM) inspection and electrical characterization of transistors has increased in difficultly. This is particularly true with early back end-of-line (BEOL) features like metal and via layers which are traditionally imaged at 3-5 keV. At these layers, this energy is capable of beam contamination, introducing electrical complications particularly with transistor probing. This electrical data is necessary to characterize subtle defects at front end-of-line (FEOL). Thus, the implementation of beam deceleration for the inspection of these layers provides a useful combination of low landing energy and higher image quality. This technique proves to aid in preserving the ability to electrically characterize any defect at the subsequent layers beneath. This increases the quality of the Physical Failure Analysis (pFA) workflow when implemented at early BEOL layers by providing higher quality images as well as preserving the electrical properties of the transistors for subtle FEOL defect characterization.

We propose an unbiased electrical fault isolation methodology for locating gate oxide breakdown failures in MOSFETs. The test vehicle involves a sub-15nm technology DRAM device which failed due to time-dependent dielectric breakdown (TDDB). This methodology introduces an implementation of Optical Beam Induced Resistance Change with no applied external bias (zero input voltage). From OBIRCH analysis, a change in current was achieved near failure site. This principle was explained based on Seebeck effect and equivalent circuit modeling of the MOSFET drain within Seebeck generator. A physical cross section using the Focused Ion Beam (FIB) revealed a gate oxide breakdown along the location of the OBIRCH spot, illustrating the benefit of an unbiased fault isolation to preserve the failure mechanism. This study proves that gate oxide breakdown site can still be located even with no external voltage applied, preserving the device condition of nanoscale DRAM, and eliminating the chances of altering the failure mechanism as a result of the applied external voltage stress.

The operation of modern semiconductor components often relies on nanoscale electronic features emerging from complicated device architectures with finely tuned composition. While the physical structure of these devices may be straightforward to image, the resulting electronic characteristics are invisible to most high-resolution imaging techniques. Here we present electron beam-induced (EBIC) imaging in the scanning transmission electron microscope (STEM) as a high-resolution imaging technique with electronic-based contrast for characterizing complex semiconductor devices. Here, as an example case, we discuss the preparation and imaging of a STEM EBIC-compatible cross section extracted from a commercial AlGaAs high electron-mobility transistor (HEMT). The device exhibits low surface leakage, as measured via electrical testing and STEM EBIC conductivity contrast. The EBIC signal in the active layer of the device is mostly confined to the InGaAs channel, indicating that the electronic structure is largely preserved following sample preparation.

Copper (Cu) material was extensively studied in the past years and widely implemented in high volume wire bonding process as a replacement of Gold (Au) material during semiconductor device fabrication. No doubt, Cu wire provide low cost alternative to gold with higher thermal and electrical conductivity, but it does pose some drawback especially after reliability stress. One of the most common problem was ball lifted after component gone through several reliability stress tests. In this paper, several FA analytical techniques and procedures will be discussed in detail to demonstrate the use of these techniques in ball lifting investigation.

This presentation provides an overview of photonic measurement techniques and their use in isolating faults and locating defects in ICs. It covers transmission, reflectance, and absorption methods, describing key interactions and important parameters and equations. Reflectance methods discussed include electro-optical probing (EOP), electro-optical frequency modulation (EOFM), and laser-voltage imaging (LVI). Absorption methods covered include those based on the absorption of light in semiconductors, as in optical beam induced current (OBIC), light-induced voltage alteration (LIVA), and laser-assisted device alteration (LADA), and those based on absorption in metals, as in thermally induced voltage alteration (TIVA), optical beam induced resistance change (OBIRCH), and thermoelectric voltage generation or Seebeck effect imaging (SEI). The presentation also covers thermoluminescence (lock-in thermography) and electroluminescence (photon emission) measurement methods and assesses hardware security risks posed by current and emerging photonic localization techniques.

This presentation provides an overview of lock-in thermography and its application in semiconductor failure analysis. It begins with a review of direct thermal imaging, IR transmission and detection, and the fundamentals of lock-in measurements. It compares and contrasts steady-state IR imaging with lock-in thermography and shows how lock-in frequency and the shape of the excitation signal can be varied to increase signal-to-noise ratio and reduce acquisition time, thereby exposing a wider range of defects. It also presents several case studies in which lock-in thermography is used to diagnose shorts and hot spots in packaged devices, electronic systems, and 3D assemblies.

This presentation is a pictorial guide to the selection and application of measurement methods for defect localization. The presentation covers passive voltage contrast (PVC), nanoprobing, conductive atomic force microscopy, and photon emission microscopy (PEM). It describes signal types, how the measurements are made, the sensing mechanisms involved, and the output that can be expected.

This paper presents a number of case studies in which various methods and tools are used to localize resistive open defects, including two-terminal IV, two-terminal electron-beam absorbed current (EBAC), electron beam induced resistance change (EBIRCH), pulsed IV, capacitance-voltage (CV) measurements, and scanning capacitance microscopy (SCM). It also reviews the advantages and limitations of each technique.

This paper demonstrates a novel defect localization approach based on EBIRCH isolation conducted from the backside of flip chips. It discusses sample preparation and probing considerations and presents a case study that shows how the technique makes it possible to determine the root cause of subtle defects, such as bridging, in flip chip failures.

An experimental study was undertaken to determine the minimum level of leakage or shorting current that could be detected by electron-beam induced resistance change (EBIRCH) analysis. A 22-nm SRAM array was overstressed with a series of gradually increasing voltage biases followed by EBIRCH scans at 1 V and 2-kV SEM imaging until fins were observed. It was found that the fins of a pulldown device could be imaged by EBIRCH at just 12 nA of shorting current, representative of a soft failure. Stressing the sample at higher voltages eventually created an ohmic short, which upon further investigation, strongly suggested that the Seebeck effect plays a significant role in EBIRCH analysis.

In this paper, we describe the difference between oscilloscope pulsing tests and waveform generator fast measurement unit (WGFMU) tests in analyzing high-resistance defects in DRAM main cells. Nanoprobe systems have various constraints in terms of pulsing whether it involves an oscilloscope or pulse generator. There are certain types of devices, such as DRAM cells, for which these systems are ineffective because saturation currents are too small. In this paper, we address this constraint and propose a new way to conduct pulsing tests using the WGFMU's arbitrary linear waveform generator in combination with an electro-optical nanoprobe.

This paper discusses advancements that have been made in scanning microwave impedance microscopy (sMIM) and how they are being used to measure various electrical properties in semiconductor devices. It explains that sMIM has a sensitivity of less than 0.1 aF and can measure minute changes in dielectric constant (k-value) and distinguish dopant levels over a wide range of concentrations with a spatial resolution of a few nm. For dielectric films and dopant levels, measurements are conveniently given in log-linear form with a repeatability well within the typical requirements for process monitoring. This, in turn, has enabled reliable quantification, where once only qualitative information was provided. The paper presents real-device results representing a wide range of measurement scenarios.

This presentation provides an overview of photonic measurement techniques and their use in isolating faults and locating defects in ICs. It covers transmission, reflectance, and absorption methods, describing key interactions and important parameters and equations. Reflectance methods discussed include electro-optical probing (EOP), electro-optical frequency modulation (EOFM), and laser-voltage imaging (LVI). Absorption methods covered include those based on the absorption of light in semiconductors, as in optical beam induced current (OBIC), light-induced voltage alteration (LIVA), and laser-assisted device alteration (LADA), and those based on absorption in metals, as in thermally induced voltage alteration (TIVA), optical beam induced resistance change (OBIRCH), and thermoelectric voltage generation or Seebeck effect imaging (SEI). The presentation also covers thermoluminescence (lock-in thermography) and electroluminescence (photon emission) measurement methods and assesses hardware security risks posed by current and emerging photonic localization techniques.

This presentation is a pictorial guide to the selection and application of measurement methods for defect localization. The presentation covers electron beam absorbed current (EBAC), electron beam induced current (EBIC), passive voltage contrast (PVC), optical and electron beam induced resistance change methods (OBIRCH and EBIRCH), lock-in thermography, photon emission microscopy (PEM), and nanoprobing. It describes how the measurements are made, the sensing mechanisms involved, and the output that can be expected.

Gate oxide breakdown has always been a critical reliability issue in Complementary Metal-Oxide-Silicon (CMOS) devices. Pinhole analysis is one of the commonly use failure analysis (FA) technique to analysis Gate oxide breakdown issue. However, in order to have a better understanding of the root cause and mechanism, a defect physically without any damaged or chemical attacked is required by the customer and process/module departments. In other words, it is crucial to have Transmission Electron Microscopy (TEM) analysis at the exact Gate oxide breakdown point. This is because TEM analysis provides details of physical evidence and insights to the root cause of the gate oxide failures. It is challenging to locate the site for TEM analysis in cases when poly gate layout is of a complex structure rather than a single line. In this paper, we developed and demonstrated the use of cross-sectional Scanning Electron Microscope (XSEM) passive voltage contrast (PVC) to isolate the defective leaky Polysilicon (PC) Gate and subsequently prepared TEM lamella in a perpendicular direction from the post-XSEM PVC sample. This technique provides an alternative approach to identify defective leaky polysilicon Gate for subsequent TEM analysis.