A reliable wire bond connection for integrated circuit devices is an important gauge in assuring a high-quality product. In comparison to pure copper wires, which are used for low-cost assembly but have oxidation problems, Palladium Coated Copper (PCC) bond wires were used to increase wire robustness, provide an advantage in applications at high temperatures, and meet criteria for good loop stiffness and hardness. However, decapsulated samples have been rejected by reliability engineering, and rework has been needed because wire discoloration was mistakenly identified as oxidized bond wires creating delays in producing the Failure Analysis (FA) result as well as wasting unnecessary resources in the process. The wrong callout happens 47.8% of the time. Through the investigation of chemical compositions, the topography of materials, and the evaluation of bond strength distribution, with some use of statistical analysis tools, this study explains how the issue was resolved. As a consequence, the wrong callout was effectively eliminated.

In this work, we investigate mushroom type phase-change material (PCM) memory cells based on Ge 2 Sb 2 Te 5 . We use low-angle annular dark field (LAADF) STEM imaging and energy dispersive X-ray spectroscopy (EDX) to study changes in microstructure and elemental distributions in the PCM cells before and after SET and RESET conditions. We describe the microscope settings required to reveal the amorphous dome in the RESET state and present an application example involving the failure analysis of a PCM test array made with devices fabricated at IBM’s Albany AI Hardware Research Center.

Fan Out - Panel Level Packaging (FO-PLP) has redistribution layers (RDLs) which connect IC to a substrate. And each layer in the RDLs is connected through copper micro-vias. Viarelated defects including via separation are very critical because they can escape from electrical test and be found in the field. So many cleaning methods have been developed to keep the target pad surface free of oxides or organic contamination before forming vias. In this paper, we present a via separation case caused by alkaline cleaning introduced before seed metal deposition for electroplating of copper. We investigated the cause by analyzing the microstructure and chemical composition using a focused ion beam (FIB) and a transmission electron microscope (TEM) equipped with an energy dispersive spectrometer (EDS). Via separation, interestingly occurred at the interface between the seed Ti and the seed Cu not the interface between the seed Ti and the target pad..Cu surface which is known to be weak. We suggest a mechanism that structural imperfections at the outer rim of via bottom and galvanic couple of titanium and copper are involved in the separation of vias. Since two dissimilar metals of Ti and Cu are in direct contact, galvanic corrosion can occur in the presence of alkaline solution and discontinuities in the seed Ti layer. We found that galvanic corrosion in the studied system can be further complicated by the existence of copper oxide and titanium oxide as well as Cu and Ti.

The composition of InGaN/AlN/GaN MQWs nano structure is anlayzed by STEM/EDS. The concentration of nitrogen in GaN materials is usually lower than that of gallium for specimen thickness larger than 50 nm due to low penetration ability of N K X-rays (0.392 KeV). The concentration of indium in the InGaN quanturm wells obtained by STEM/EDS analysis is always much lower its real value. This concentration dilution in this 3 nm structure results from the effect of electron beam broadening, and can be improved to a certain level by reducing specimen thickness, C2 aperture, and dwell time, with a sacrifice in signal intensity.

We describe a technique for mapping the distribution and concentrations of trace elements, most notably with capabilities of achieving 1-10 parts per million sensitivities within 1 second and at <8 μm resolution. The technique features an innovative, high flux microstructured x-ray source and a new approach to x-ray optics comprising a high efficiency twin paraboloidal x-ray mirror lens. The resulting ability to acquire dramatically higher sensitivities and resolution than conventional x-ray fluorescence approaches, and at substantially higher throughput enables powerful compositional mapping for failure analysis, process development, and process monitoring.

Abnormal inline defects were caught after nitride spacer etching processes. Detailed MEBES layout checking and inline SEM inspection revealed that such defects always appeared at the boundaries in between PFETs and NFETs regions. The microstructure and chemical composition of the defects were analyzed in detail by various TEM imaging and microanalysis techniques. The results indicated that the defect possessed core-shell structure, with oxide core and nitride shell. Based on the TEM failure analysis results and manufacturing processes, we conclude that the defects originated from PR fencing due to the PR hardening during PFET and NFET LDD/Halo implantation. The oxide core was generated during oxide spacer formation using an ozone-TEOS process, which was responsible for the nitride spacer under-etch issue.

The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.