This paper presents a root cause analysis case study of defective Hall-effect sensor devices. The study identified a complex failure mode caused by chip-package interaction, which has a similar signature to discharging defects such as ESDFOS. However, the study revealed that the defect was induced by local mechanical force applied to IC structures due to the presence of large irregular-shaped filler particles within the mold compound. Extensive failure analysis work was conducted to identify the failure mode, including the development of a new backside analysis strategy to preserve the mold compound during IC defect localization and screening. A combination of different failure analysis techniques was used, including CMP delayering, PFIB trenching, SEM PVC imaging, and large area FIB cross-sectioning. The study found that the mold compound of the package caused thermos-mechanical strain onto the silica filler particle due to epoxy shrinkage during the molding process. Additionally, extra-large, irregularly shaped filler particles (called twin particles), located on top of the chip surface, can cause locally high compression stresses onto the IC layers, initiating cracks in the isolation layers under certain conditions forming a leakage path over the time. Thermo-mechanical finite element analysis was applied to verify the mechanical load condition for these large irregular-shaped filler particles. As a result, an additional polyimide layer was introduced onto the IC to mitigate the mechanical stress of mold compound particles to avoid this failure mode.

Several failures in Chip-On-Lead (COL) package from the customer were returned for Failure Analysis (FA). Containment activities were able to find similar failures. The connectivity of the silicon die to the leads uses gold wire. The die is in live bug position with respect to the package and is being held in place using non-conductive die attach epoxy. The identification of the Failure Mechanism (FMECH) utilized analysis flow involving non-destructive and destructive FA techniques. A hairline crack was found on the die between the two (2) corner pins. Based on lot history reviews, hairline die crack had a very low detectability at electrical test. Further collaboration with the process owners showed the need to identify the crack initiation, propagation and the factors that could result to this FMECH. Analysis of fracture or fractography was utilized in identifying the crack initiation point and propagation. Due to low detectability, identifying the factors resulting to die crack would require several evaluations and process mappings. Finite element analysis (FEA) was utilized to create models and simulation to identify factors that would result to highly stressed area identified through fractography. These additional data for the hairline crack were vital on the identification of root cause and formulation of corrective/preventive actions.

Global thinning is a technique that enables backside failure analysis and radiation testing. In some devices, it can also lead to increased thresholds for single-event latchup and upset. In this study, we examine the impacts of global thinning on 28 nm node FPGAs. Test devices are thinned to 50, 10, and 3 μm via CNC milling. Lattice damage, in the form of dislocations, extends about 1 μm below the surface, but is removed by polishing with colloidal SiO2. As shown by finite-element modeling, thinning increases compressive global stress in the Si while solder bumps (in flip-chip packages) increase stress locally. The results are confirmed by stress measurements obtained through Raman spectroscopy, although more complex models are needed to account for nonlinear effects in devices thinned to 3 μm and heated to 125°C. Thermal imaging shows that increased local heating occurs with increased thinning, but the maximum temperature difference across the 3-μm die is less than 2°C. Ring oscillators throughout the FPGA fabric slow about 0.5% after thinning and another 0.5% when heated to 125°C, which is attributed to stress changes in the Si.

We present a new method for backside integrated circuit (IC) magnetic field imaging using Quantum Diamond Microscope (QDM) nitrogen vacancy magnetometry. We demonstrate the ability to simultaneously image the functional activity of an IC thinned to 12 µm remaining silicon thickness over a wide fieldof- view (3.7 x 3.7 mm 2 ). This 2D magnetic field mapping enables the localization of functional hot-spots on the die and affords the potential to correlate spatially delocalized transient activity during IC operation that is not possible with scanning magnetic point probes. We use Finite Element Analysis (FEA) modeling to determine the impact and magnitude of measurement artifacts that result from the specific chip package type. These computational results enable optimization of the measurements used to take empirical data yielding magnetic field images that are free of package-specific artifacts. We use machine learning to scalably classify the activity of the chip using the QDM images and demonstrate this method for a large data set containing images that are not possible to visually classify.

The continuously growing demands in high-density memories drive the rapid development of advanced memory technologies. In this work, we investigate the HfOx-based resistive switching memory (ReRAM) stack structure at nanoscale by high resolution TEM (HRTEM) and energy dispersive X-ray spectroscopy (EDX) before and after the forming process. Two identical ReRAM devices under different electrical test conditions are investigated. For the ReRAM device tested under a regular voltage bias, material redistribution and better bottom electrode contact are observed. In contrast, for the ReRAM device tested under an opposite voltage bias, different microstructure change occurs. Finite element simulations are performed to study the temperature distributions of the ReRAM cell with filaments formed at various locations relative to the bottom electrode. The applied electric field as well as the thermal heat are the driving forces for the microstructure and chemical modifications of the bottom electrode in ReRAM deceives.

Scanning Microwave Impedance Microscopy (sMIM) can be used to characterize dielectric thin films and to quantitatively discern film thickness differences. FEM modeling of the sMIM response provides understanding of how to connect the measured sMIM signals to the underlying properties of the dielectric film and its substrate. Modeling shows that sMIM can be used to characterize a range of dielectric film thicknesses spanning both low-k and medium-k dielectric constants. A model system consisting of SiO2 thin films of various thickness on silicon substrates is used to illustrate the technique experimentally.

This paper presents the electrical model of an NMOS transistor in 90nm technology under 1064nm Photoelectric Laser Stimulation. The model was built and tuned from measurements made on test structures and from the results of physical simulation using Finite Element Modeling (TCAD). The latter is a useful tool in order to understand and correlate the effects seen by measurement by given a physical insight of carrier generation and transport in devices. This electrical model enables to simulate the effect of a continuous laser wave on an NMOS transistor by taking into account the laser’s parameters (i.e. spot size and power), spatial parameters (i.e. the spot location and the NMOS’ geometry) and the NMOS’ bias. It offers a significant gain of time for experiment processes and makes it possible to build 3D photocurrent cartographies generated by the laser on the NMOS, in order to predict its response independently of the laser beam location.

The semiconductor industry is recognizing an increasing need to define the compatibility of various products joined in package-on-package configuration by solder reflow. Within the scope of the application, this paper discusses: sample preparation; warpage data collection methods; extraction of usable images and numerical data from the measurements; creation of visual warpage patterns for the top and bottom components of stacked package sets; mathematical determination of variation or separation of parts at critical locations during reflow; and finite element analysis of parts and processes to understand and predict reactions to design changes.

Several considerations related to the implementation of the thermal laser stimulation method (OBIRCH, TIVA) in a failure analysis laboratory will be discussed. At the CNES (French Space Agency), we implemented this method on a dual system which includes an emission microscope and a laser-scanning microscope. The amplifier used for amplifying the weak voltage or current variations caused by thermal laser stimulation was shown to be a key factor. The design of such a low noise, high gain and fast voltage amplifier is described. From a 3D finite element ANSYS model of the thermal laser stimulation effect combined with three practical case studies we show that thermal laser stimulation is a rapid and precise method for localizing metallic short type faults in ICs. In order to interpret the thermal laser stimulation signal, a simple CMOS inverter model is also presented.

Thermal properties are critical to the performance of micromachined silicon bolometers. In order to verify thermal models of the device, a means of measuring the local temperature distribution over the element is required, as it is heated by passing current through a thin film titanium meander. Because of the very low thermal mass of the membrane a non-contact method of temperature measurement is needed. Most conventional thermal imaging systems operate in the wavelength range 5-15 μm and offer poor spatial resolution but in this work an infrared microscope, operating at shorter wavelengths, was used. The microscope comprises an objective lens which focuses radiation onto a cooled (77K) cadmium mercury telluride focal plane array sensitive over the range 800 nm to 2500nm. For this application a bandpass filter centered at 2150 nm was used. Good agreement was obtained between finite element modeling of the temperature distribution, using ANSYS, and the measured data.

Failure analysis and finite-element analysis were used in conjunction to determine the cause of zener diode failures. A mechanical/plasma depot method was developed for the plastic-encapsulated SMB package and used to observe the presence of remelted extruded solder material on the die surface. That material provided a conductive path which manifested electrically as premature breakdown. Transient-thermal finite-element analysis was then used to show that a recent change of in-house surge test parameters could result in part temperatures during surge testing in excess of the solder melting temperature. These efforts lead to a respecification of the in-house surge test duration which resolved the problem.