In wafer fabrication, a silicon nitride (Si3N4) layer is widely used as passivation layer. To qualify the passivation layers, traditionally chemical recipe PAE (H3PO4+ HNO3) is used to conduct passivation pinhole test. However, it is very challenging for us to identify any pinholes in the Si3N4 layer with different layers underneath. For example, in this study, the wafer surface is Si3N4 layer and the underneath layer is silicon substrate. The traditional receipt of PAE cannot be used for passivation qualification. In this paper, we will report a new recipe using KOH solution to identify the pinhole in the Si3N4 passivation layer.

This paper placed a strong emphasis on the importance of applying Systematic Problem Solving approach, deep dive and use of right/appropriate FA approach/tools that are essentially critical to FA analysts to understand the “real” root cause. A case of low yield with polar failing pattern was seen and matched well with the Al Pad etch E chuck configuration. Customer also reported of passivation crack issue at the solder bumps. All these evidences suggested the root cause was related to wafer fabrication issue. However, it was through a strong “inquisitive” mindset coupled with the essence of such strong problem solving approach that led to uncover the actual root cause. Although customer test condition was not able to be duplicated due to limited information available in foundry industry, a four point probing alternative method was engaged to overcome this limitation. Unlike typical case, the AlOx thickness was comparable for bad and good dies. Further in depth analysis subsequently revealed the higher O content in the AlOx for the bad dies that was the real culprit for the higher bump resistance. This paper highlights the job of FA analyst is not simply finding defect but also plays a catalyst role in root cause/failure mechanism understanding by providing supporting FA evidence (electrically / physically) to Fab. It would serve as a good reference to wafer Fab that encountered such issue.

Passivation damage, a common failure mode in microelectronics circuitry, can be easily identified by optical inspection in the form of a local 'discoloration' after exposing the die to a chemical that would penetrate through the crack and attacks metal lines. Unfortunately, this process destroys evidence of what damaged the passivation, since it attacks the damaged region. As a result, in many cases, the mechanism by which the passivation damage occurred is unclear. This problem is addressed in this paper by a procedure to examine passivation damage by transmission electron microscopy (TEM) of a cross-section sample prepared from the backside and without exposing the die from the top side. The backside approach was successfully used to assign the root cause of the passivation damage to packaging process. A topside approach to characterize the passivation damaged region can result in destruction of evidence at the defect location.

Various detector chips in optocoupler devices have a thin indium tin oxide (ITO) film deposited over the passivation. This transparent, conductive film is found over the photodetecting area of the die. When this film is electrically connected to ground potential through contacts, it acts as a shield to avoid inversion failures by sinking any charge buildup to ground. In order to perform a full electrical failure analysis on these optocoupler detector chips, the ITO layer must be removed. An extensive search found numerous papers on etching this film over glass substrates, but no known technique was found to selectively remove the ITO layer on a packaged die. This paper discusses an approach to remove this film using an argon gas etch technique. The ideal characteristics of any process used to remove this film on a finished die would be to completely etch the ITO layer, electrically isolating it from ground, while leaving the underlying passivation and metallization fully intact. This would allow for further electrical failure analysis of the die without causing additional damage or affecting the failure mechanism. The results of an experiment using various chemical and gas etchants found that an argon gas etch would remove the ITO layer while only slightly etching the phosphosilicate glass (PSG) passivation beneath. Electrical failure analysis of the die continued at this point, and a subsequent buffered oxide etch (BOE) removed the remaining passivation, leaving the exposed metallization and oxide completely intact. This technique has been used successfully on device failures to find passivation contamination shorting the aluminum metallization to the ITO film.

Temperature measurements on passivated electronic devices and the determination of the local thermal conductivity using the Scanning Thermal Microscope demonstrate promising possibilities to use this system as a tool for thermal diagnostics as well as for the failure analysis. Since doping concentration affects the thermal conductivity (k) due to the free carriers introduced, we propose the SThM as a potential dopant-profiling tool. To correlate doping concentration and thermal conductivity, we have mapped out the thermal conductivity of decreasing Boron-doped and Phosphorus-doped staircase silicon substrates and compared these data to the corresponding doping profile from ID Secondary ion mass spectroscopy (SIMS). To demonstrate the ability of the SThM technique to analyze both thermal features - temperature distribution and quantitative thermal conductivity - of an electronic device, we investigated properties of an NMOS device.

As integrated circuits’ geometry are reduced by about 0.7 for each new generation, failure analysis becomes more challenging in fault isolation and physical deprocessing to determine the root cause of the failure. It is impossible to deprocess the device by conventional wet-etch method as metallization tends to be etched or lifted off using all known wet chemicals. Currently the deprocessing techniques can be classified into two categories: dry-etch plus mechanical polishing and full dry-etched methods. In Chartered a new deprocessing technique by combining selective wet-etching of passivation and Inter Metal Dielectric (IMD) layers and mechanical lapping/polishing have been developed. Selective removal of passivation and IMD layers is of major importance in failure analysis of semiconductor devices. The key objective of this technique is to etch away passivation and IMD layers without attacking any metallization. This new deprocessing technique enables failure analyst to delayer by wet-etch again even those submicron devices. It avoided dry etch related problem such as selectivity, temperature control, etch rate stability, RIE grass, side wall polymer and end point detection…etc. It offers a cheaper alternative method for deprocessing when the plasma etcher is not available.

Mechanical stress problems in integrated circuit devices are becoming more severe as the number of metal interconnect levels increases and new materials such as low-k dielectrics are introduced. We studied dielectric cracking in a four-level Al-Cu interconnect structure that uses hydrogen silsesquioxane (HSQ), a low dielectric constant (low-k) material. The cracks extended down through the passivation layers to the HSQ layer. For the first time we report on passivation dielectric cracks directly related to the level of residual fluorine in a plasma enhanced chemical vapor deposition (PECVD) reactor. It is shown that a silicon nitride pre-coat deposition removes fluorine (F) from the reactor ambient and prevents the dielectric cracks.

Stacked-chip scale package (S-CSP) is a new packaging technology introduced in the memory components market to effect chip miniaturization, a challenging trend in semiconductor assembly. The package is built by molding two stacked dice (Flash and SRAM) on bismaleimide triazine (BT) substrate. As this novel packaging technology offers solution to the challenge, it also poses complexity in the field of failure analysis in cases that the bottom die is the interest. Deprocessing these stacked dice while maintaining the functionality of the bottom die will be explained in detail. Prior the conduct of failure analysis (FA) and fault isolation (FI), deprocessing the failing unit containing only one die normally consists of chemical decapsulation. S-CSP sample preparation also adheres to this treatment in case the top die is the aim for analysis. On the other hand, if the concern shifts to the bottom die, sequential techniques involving precision polishing to die-to-die adhesive layer, chemical etching of adhesive and residual molding compound, and rebonding the bottom die on ceramic interposer, are employed. With the rebonded S-CSP bottom die, fault isolation could be performed further. This paper will also feature the mechanism behind the blown-up failure, a power test failure in memory devices, encountered during the package development when two types of die-to-die adhesives were selected and used. Consistent with the results of electrical characterization suggesting that S-CSP bottom die as the failing die, passivation damage is uncovered on the bottom die upon separation of the stacked dice. Material comparison points out that the hard, angular glass fillers of the die-to-die adhesive induce the damage. Polymer-filled adhesive performs better than the glass-filled adhesive as indicated by the results of the package characterization. Generally, this case exemplifies a packaging material-related failure. Moreover, the paper could serve as a reference material in the event that feasibility of packaging non-memory components in S-CSP is to be evaluated. The developed methodology of recovering the S-CSP bottom die would be a keystone in proacting for its FA readiness.

Selective removal of silicon nitride passivation layers is of major importance in failure analysis of semiconductor devices. Typical applications are: cleaning of the die surface for optical microsccjpy and for removal of superficial contamination, electron microscopy, liquid crystals, voltage contrast, electron beam testing, mechanical microprobing, and . selective layer-by-layer strip. A new wet-etch for silicon nitride passivation layers has been developed, which is fully selective! over aluminum metallization and which preserves full device functionality after passivation removal. For the first time in the failure analysis literature, the chemical recipe and the etching procedure are given in details. This etchant has been experimented for more than two years in many failure analysis laboratories on a wide spectrum of discrete and integrated semiconductor devices, always with excellent results. Its capability and efficiency are illustrated by two failure analysis case histories.

Optimization of the passivation scheme for a 0.35 μm TLM process is presented. The passivation layer is required to provide mechanical and chemical protection during the assembly and packaging process and long term environmental protection. The passivation scheme was optimized by testing a product-like test vehicle at accelerated environmental stress conditions of high humidity and high temperature. The initial passivation scheme showed a unique electrical test signature - a voltage dependent failure with open circuit at low voltage/pass at high voltage. Advanced wafer-level failure analysis techniques and equipment were used to isolate and identify the failure site. Further cross-section analysis revealed that the failure site was a fracture across a via and adjoining IMO. This cracking was attributed to stress corrosion fracture of the IMO based on root cause analysis. This hypothesis required a path for moisture to the stressed IMO-2 location to cause the fracture. The moisture path was identified by further analysis and process changes to eliminate this were implemented. All subsequent parts passed the accelerated environmental tests confirming the stress corrosion fracture hypothesis.