Novel sample preparation techniques have been developed for Three-Dimensional Heterogeneously Integrated (3DHI) devices to enable precise failure analysis while protecting adjacent components. Traditional grinding and polishing methods risk damaging surrounding areas when tool bits extend beyond the target region. Using the VarioMill system's high-precision stages (±1µm accuracy), we introduce three key innovations: a helical grinding approach for accessing die centers, an extended tool bit technique for processing rectangular corners, and enhanced polishing protocols. These methods allow for targeted sample preparation of individual dies or specific die regions while completely preserving adjacent components. The techniques are particularly valuable for complex, densely packed 3DHI devices where conventional preparation methods pose significant risks of collateral damage.

Cross-sectional analysis plays a crucial role in failure analysis for the identification of root causes associated with implants or junction profiles. Traditionally, this step involves junction staining. Recently, Electron Beam Induced Current (EBIC) analysis has emerged as a valuable alternative, offering the key advantage of visualizing various implantations and junction profiles through non-chemical means. This paper presents an innovative sample preparation technique for cross-sectional EBIC analysis, incorporating an additional step of FIB (Focused Ion Beam) grooving at the target site before cross-sectional polishing. Unlike conventional methods that involve laborious and time-consuming fine cross-sectional polishing, our approach enhances precision and efficiency. With the elimination of the need for extensive polishing, direct access to the target is achieved after rough polishing, thereby expediting the analytical process.

Mechanical sample preparation is a crucial and indispensable step in modern failure analysis (FA). Traditional methods excel in reducing bulk silicon to thicknesses of several tens of micrometers. However, contemporary demands necessitate sample preparation below 10 µm or even below 5 µm, which is challenging, time-consuming, and requires an expensive toolset and advanced operator expertise. Existing methods, which rely on mechanical components for bulk removal, induce mechanical stress and microcracks that can alter the electrical characteristics of the sample. Maintaining the sample's electrical behavior is essential for accurate FA. This paper introduces a novel approach to sample preparation that employs concepts from wafer-level chemical mechanical polishing (CMP). This method ensures reliable sample preparation without introducing microcracks, accurately halts material removal at the shallow trench isolation (STI) – or deep STI - level, and maintains the sample's electrical functionality. The proposed approach is discussed in detail, including successful thinning of various sample types to the STI level, which were subsequently tested for electrical functionality.

The ability to precisely remove the internal structures of a semiconductor device, layer-by-layer, is a necessity for semiconductor research and failure analysis investigation. Currently, numerous techniques are used, such as mechanical polishing, chemical etching, and gas assisted plasma focused ion beam (FIB) milling. However, all of these techniques have limitations in that they are unable to: (1) delayer a millimeter-scale area with nanometer-scale uniformity, (2) rapidly remove thick (>300 nm) device layers, or (3) perform automatic and accurate end pointing, which is challenging on thin (≤300 nm) device layers.

Nowadays, semiconductor components are widely used in home electronic appliances, vehicles, industrial motor controls and beyond. The performance and reliability of these components are becoming more crucial and critical. Generally, a semiconductor component consists of lead frames, wires, dies and die attaches. Within the die, the die backside metallization, also known as “BSM,” plays an important role in electronic component manufacturing. The BSM is a layer that promotes good adhesion, electrical properties and long-term stability as a conductive pathway to the circuits. As such, the inspection on BSM is needed to ensure robustness. Several conventional methods have been developed to analyze the die backside metallization. In this paper, we will discuss the inspection on backside metallization and comparison among five sample preparation methods: mechanical cross section with ion milling, mechanical cross section with FIB cleaning, die frontside decapsulation with FIB cut from die surface and FIB cut from die sidewall, and component frontside lapping with FIB from the remaining silicon. Result comparison will be discussed in case studies and the advantages and disadvantages of the five methods will be compared.

As advanced device technologies scale to 5nm with dimensions getting smaller and materials change, it is difficult to control the sample preparation delayering end pointing by polishing. Therefore, it requires an alternative solution such as Xe+ PFIB (Plasma Focused Ion beam) Microscopy for accurate delayering control. PFIB can be used for planar Failure Analysis (FA) delayering but also for nanoprobing sample preparation. This paper introduces the detail of nanoprobing sample preparation by PFIB and discusses nanoprobing results on 5nm FinFET technology.

Microscopic imaging and characterization of semiconductor devices and material properties often begin with a sample preparation step. A variety of sample preparation methods such as mechanical lapping and broad ion beam (BIB) milling have been widely used in physical failure analysis (FPA) workflows, allowing internal defects to be analyzed with high-resolution scanning electron microscopy (SEM). However, these traditional methods become less effective for more complicated semiconductor devices, because the cross-sectioning accuracy and reliability do not satisfy the need to inspect nanometer scale structures. Recent trends on multi-chip stacking and heterogenous integration exacerbate the ineffectiveness. Additionally, the surface prepared by these methods are not sufficient for high-resolution imaging, often resulting in distorted sample information. In this work, we report a novel correlative workflow to improve the cross-sectioning accuracy and generate distortion-free surface for SEM analysis. Several semiconductor samples were imaged with 3D X-ray microscopy (XRM) in a non-destructive manner, yielding volumetric data for users to visualize and navigate at submicron accuracy in three dimensions. With the XRM data to serve as 3D maps of true package structures, the possibility to miss or destroy the fault regions is largely eliminated in PFA workflows. In addition to the correlative workflow, we will also demonstrate a proprietary micromachining process which is capable of preparing deformation-free surfaces for SEM analysis.

Planar deprocessing is a vital failure analysis technique for semiconductor devices. The basic concept is to expose an area of interest (AOI) by removing unnecessary material while maintaining planarity and surface evenness. Finger deprocessing is a widely used material removal technique, particularly for fin field-effect transistors (FinFETs). Here, success depends on certain factors, one of which is the location of the AOI. If the AOI is near the edge of the chip, finger deprocessing can be very difficult because material removal rates are much higher there than at the center of the chip. Plasma focused ion beam (PFIB) planar deprocessing is the preferred solution in such cases, but many labs cannot afford a PFIB system. To address this challenge, a sample preparation method has been developed that uses dummy chips to effectively eliminate edges. With dummy chips placed edge-to-edge with test chips, planar deprocessing can be achieved using conventional finger deprocessing techniques. This paper describes the newly developed method, step by step, and presents two examples demonstrating its use.

Convention hand polishing, which is widely used for delayering, is becoming increasingly difficult as metal lines and stacks in semiconductor devices get thinner. For one thing, endpointing at the exact targeted layer and region of interest is a major challenge. The presence of cobalt and its propensity to oxidize, thus complicating electrical measurements, is another challenge. In this study, the authors demonstrate an alternative delayering method based on plasma focused ion beam (PFIB) milling aided by DX gas. The workflow associated with the new method is more efficient than that of conventional hand polishing and can help prevent cobalt oxidation.

This paper describes a procedure for preparing packaged GaN devices for photon emission microscopy from the backside, which has proven to be an effective method for isolating faults. The deprocessing technique was developed for GaN devices formed on thick p ++ silicon substrates mounted in quad-flat no-lead (QFN) packages connected by gold wires. It consists of mechanical polishing, which removes backside metal and packaging material, and selective etching, which quickly etches the silicon while leaving the gold wires intact for electrical measurements. The authors describe each step of the process in detail and explain how emission spots are marked with a UV laser and analyzed in a FIB-SEM system to determine the underlying cause of failure.

This paper presents a large-volume workflow for fast failure analysis of microelectronic devices. The workflow incorporates a stand-alone ps-laser ablation tool and a FIB-SEM system. As implemented, the picosecond laser is used to quickly remove large volumes of bulk material while the Xe plasma FIB provides precise end-pointing to the feature of interest and fine surface polishing after laser ablation. The paper presents several application examples, including a full workflow to prepare artefact-free, delamination-free cross-sections in an AMOLED mobile display and the preparation of devices and packages (including flip chips) of varying size. It also covers related issues such as CAD navigation, data correlation, and the use of bitmap overlays for end-pointing.

This paper describes how electron beam induced current (EBIC) analysis is used to determine the doping profile of p-n junctions and identify defective devices. The limitations of both chemical etching and EBIC are discussed as is the use of ion milling as a potential method for enhancing resolution. The findings in this paper add to the understanding of EBIC and provide insights to further improvements in its use in failure analysis.

This paper explains how the authors determined the cause of a fast-to-rise failure discovered during scan chain testing of an image sensor. The failed device was mounted on a portable card that facilitates transfer between test platforms in an electro-optical probing (EOP) system. Initial fault localization was conducted through backside PEM, but the results were inconclusive. The part was then analyzed on a digital scan chain tester to check for flaws in the daisy chain of shift registers. Through broken scan chain analysis, the potential cause of the problem (a failing flip-flop) was narrowed down to a few chain links and ultimately pinpointed using EOP fault isolation techniques. The failed device was then deprocessed by parallel lapping and analyzed in a SEM, revealing a broken poly gate as the physical cause of failure.

Integrated circuit (IC) delayering workflows are highly reliant on operator experience to determine processing end points. The current method of end point detection during IC delayering uses qualitative correlations between the thickness and color of dielectric films observed via optical microscopy. The goal of this work is to quantify this relationship using computer vision. As explained in the paper, the authors trained a convolutional neural network to estimate the thickness of dielectric films based on images and measurements recorded during processing. The trained vision model explained 39% of the variance in dielectric film thickness with a mean absolute error of approximately 47 nm. The paper describes the entire workflow, including verification testing, and addresses the primary sources of error.

Global thinning is a technique that enables backside failure analysis and radiation testing. In some devices, it can also lead to increased thresholds for single-event latchup and upset. In this study, we examine the impacts of global thinning on 28 nm node FPGAs. Test devices are thinned to 50, 10, and 3 μm via CNC milling. Lattice damage, in the form of dislocations, extends about 1 μm below the surface, but is removed by polishing with colloidal SiO2. As shown by finite-element modeling, thinning increases compressive global stress in the Si while solder bumps (in flip-chip packages) increase stress locally. The results are confirmed by stress measurements obtained through Raman spectroscopy, although more complex models are needed to account for nonlinear effects in devices thinned to 3 μm and heated to 125°C. Thermal imaging shows that increased local heating occurs with increased thinning, but the maximum temperature difference across the 3-μm die is less than 2°C. Ring oscillators throughout the FPGA fabric slow about 0.5% after thinning and another 0.5% when heated to 125°C, which is attributed to stress changes in the Si.

Physical FA innovations in advanced flip-chip devices are essential, especially for die-level defects. Given the increasing number of metal layers, traditional front-side deprocessing requires a lot of work on parallel lapping and wet etching before reaching the transistor level. Therefore, backside deprocessing is often preferred for checking transistor-level defects, such as subtle ESD damage. This paper presents an efficient technique that involves precise, automated die thinning (from 760µm to 5µm), high-resolution fault localization using a solid immersion lens, and rigorous KOH etch. Using this technique, transistor-level damage was revealed on advanced 7nm FinFET devices with flip-chip packaging.

Three-dimensional device (FinFET) doping requirements are challenging due to fin sidewall doping, crystallinity control, junction profile control, and leakage control in the fin. In addition, physical failure analyses of FinFETs can frequently reach a “dead end” with a No Defect Found (NDF) result when channel doping issues are the suspected culprit (e.g., high Vt, low Vt, low gain, sub-threshold leakage, etc.). In new technology development, the lack of empirical dopant profile data to support device and process models and engineering has had, and continues to have, a profound negative impact on these emerging technologies. Therefore, there exists a critical need for dopant profiling in the industry to support the latest technologies that use FinFETs as their fundamental building block [1]. Here, we discuss a novel sample preparation method for cross-sectional dopant profiling of FinFET devices. Our results show that the combination of low voltage (<500eV), shallow angle (~10 degree) ion milling, dry etching, and mechanical polishing provides an adequately smooth surface (Rq<5Å) and minimizes surface amorphization, thereby allowing a strong Scanning Capacitance Microscopy (SCM) signal representative of local active dopant (carrier) concentration. The strength of the dopant signal was found to be dependent upon mill rate, electrical contact quality, amorphous layer presence and SCM probe quality. This paper focuses on a procedure to overcome critical issues during sample preparation for dopant profiling in FinFETs.

On mechanically polished cross-sections, getting a surface adequate for high-resolution imaging is sometimes beyond the analyst’s ability, due to material smearing, chipping, polishing media chemical attack, etc.. A method has been developed to enable the focused ion beam (FIB) to re-face the section block and achieve a surface that can be imaged at high resolution in the scanning electron microscope (SEM).

Dopants imaging using scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy are used for identifying doped areas within a device, the latter being analyzed either in a top view or in a side view. This paper presents a sample preparation workflow based on focused ion beam (FIB) use. A discussion is then conducted to assess advantages of the method and factors to monitor vigilantly. Dealing with FIB machining, any sample preparation geometry can be achieved, as it is for transmission electron microscopy (TEM) sample preparation: cross-section, planar, or inverted TEM preparation. This may pave the way to novel SCM imaging opportunities. As FIB milling generates a parasitic gallium implanted layer, a mechanical polishing step is needed to clean the specimen prior to SCM imaging. Efforts can be conducted to reduce the thickness of this layer, by reducing the acceleration voltage of the incident gallium ions, to ease sample cleaning.

This paper provides an innovative root cause failure analysis method that combines multiple failure analysis (FA) techniques to narrow down and expose the shorting location and allow the material analysis of the shorting defect. It begins with a basic electrical testing to narrow down shorting metal layers, then utilizing mechanical lapping to expose over coat layers. This is followed by optical beam induced resistance change imaging to further narrow down the shorting location. Scanning electron microscopy and optical imaging are used together with focused ion beam milling to slice and view through the potential shorting area until the shorting defect is exposed. Finally, transmission electron microscopy (TEM) sample is prepared, and TEM analysis is carried out to pin point the root cause of the shorting. This method has been demonstrated successfully on Western Digital inter-metal layers shorting FA.