The challenges keep rising for fault isolation and failure analysis (FIFA) for the advanced semiconductor devices fabricated via integrated processes. Perceiving that defects randomly occurred during IC manufacturing contribute primarily to the device failures in comparison to those caused by harsh service environmental, we focus our efforts on fixing the defect issues in the processes, expecting a significant portion of the device failures may be prevented. A case study here demonstrates the procedure for fixing an inline defect issue via improving tool maintenance for the chemical-mechanical polishing (CMP) process. Through a correlative physical and chemical analysis down to atomic scale, a 10 nm diamond particle and a 10 nm metallic debris damaging one of the metal interconnect layers were defined. The analysis led to pinpointing the issue to a metal CMP process. By examining the process operation and the tool configuration, we located the diamond-missing sites on a pad-conditioning disk made with embedded diamond grits in a metal matrix. Preventive countermeasure were implemented to avoid the same defect recurring via resetting the disk life and maintenance.

This paper presents a root cause analysis case study of defective Hall-effect sensor devices. The study identified a complex failure mode caused by chip-package interaction, which has a similar signature to discharging defects such as ESDFOS. However, the study revealed that the defect was induced by local mechanical force applied to IC structures due to the presence of large irregular-shaped filler particles within the mold compound. Extensive failure analysis work was conducted to identify the failure mode, including the development of a new backside analysis strategy to preserve the mold compound during IC defect localization and screening. A combination of different failure analysis techniques was used, including CMP delayering, PFIB trenching, SEM PVC imaging, and large area FIB cross-sectioning. The study found that the mold compound of the package caused thermos-mechanical strain onto the silica filler particle due to epoxy shrinkage during the molding process. Additionally, extra-large, irregularly shaped filler particles (called twin particles), located on top of the chip surface, can cause locally high compression stresses onto the IC layers, initiating cracks in the isolation layers under certain conditions forming a leakage path over the time. Thermo-mechanical finite element analysis was applied to verify the mechanical load condition for these large irregular-shaped filler particles. As a result, an additional polyimide layer was introduced onto the IC to mitigate the mechanical stress of mold compound particles to avoid this failure mode.

When aiming for extreme thinning of the bulk silicon down to the shallow trench isolation (STI) level, endpoint determination is a challenging task. Here, we present a novel approach providing reliable access to the STI level of single dies. Therefore, we transfer the wafer-based CMP process to be applicable to single dies on a table-top machine. In a first step, the developed process is applied to the whole IC backside simultaneously. Using a highly selective slurry with a material removal ratio from Si to SiO of more than 500:1 ensures that the STI level remains intact. Two types of samples have been prepared for experiments performed for this paper. A 115mm x 80mm flip-chip bonded device with a bulk silicon thickness of 500μm has been prepared to STI level within less than 4 hours.

Integrated circuit (IC) delayering workflows are highly reliant on operator experience to determine processing end points. The current method of end point detection during IC delayering uses qualitative correlations between the thickness and color of dielectric films observed via optical microscopy. The goal of this work is to quantify this relationship using computer vision. As explained in the paper, the authors trained a convolutional neural network to estimate the thickness of dielectric films based on images and measurements recorded during processing. The trained vision model explained 39% of the variance in dielectric film thickness with a mean absolute error of approximately 47 nm. The paper describes the entire workflow, including verification testing, and addresses the primary sources of error.

Many semiconductor products are manufactured with mature technologies involving the uses of aluminum (Al) lines and tungsten (W) vias. High resistances of the vias were sometimes observed only after electrical or thermal stress. A layer of Ti oxide was found on such a via. In the wafer processing, the post W chemical mechanical planarization (WCMP) cleaning left residual W oxide on the W plugs. Ti from the overlaying metal line spontaneously reduced the W oxide, through which Ti oxide formed. Compared with W oxide, the Ti oxide has a larger formation enthalpy, and the valence electrons of Ti are more tightly bound to the O ion cores. As a result, the Ti oxide is more resistive than the W oxide. Consequently, the die functioned well in the first test in the fab, but the via resistance increased significantly after a thermal stress, which led to device failure in the second test. The NH4OH concentration was therefore increased to more effectively remove residual W oxide, which solved the problem. The thermal stress had prevented the latent issue from becoming a more costly field failure.

This work outlines a case study of charge-induced damage to SOI wafers that caused gate leakage in discrete transistors and static leakage in packaged integrated circuits (ICs). The consequential yield fallout occurred primarily at wafer center. Electrical, optical, and laser-based failure analysis techniques were used to characterize the damage and determine root cause of electrical failure. The failure mechanism was localized to a rinse step during chemical mechanical planarization (CMP). Furthermore, both current-voltage (IV) sweeps and characteristic spatial patterns generated by thermally-induced voltage alteration (TIVA) were used to capture the trends on both packaged ICs and SOI wafers for this type of charge-induced damage; this led to quick identification of another source of charge-induced damage that affected the post-fab yield.

In this work, we present TEM failure analysis of two typical failure cases related to metal voiding in Cu BEOL processes. To understand the root cause behind the Cu void formation, we performed detailed TEM failure analysis for the phase and microstructure characterization by various TEM techniques such as EDX, EELS mapping and electron diffraction analysis. In the failure case study I, the Cu void formation was found to be due to the oxidation of the Cu seed layer which led to the incomplete Cu plating and thus voiding at the via bottom. While in failure case study II, the voiding at Cu metal surface was related to Cu CMP process drift and surface oxidation of Cu metal at alkaline condition during the final CMP process.

Direct surface bonding of wafers in 3D integration requires perfectly smooth surfaces, with roughness values below 1 nm, usually characterized with Atomic Force Microscopy. An alternative technique, Digital Holography Microscopy is evaluated here and shown to be precise enough to differentiate adequate wafers, that is chemical mechanical polished, from non treated ones.

The back-end-of-line (BEOL) structure of current IC devices fabricated for advanced technologies is composed of film stacks with multiple interfaces. The requirement of high interfacial strength is therefore necessary between the different layers in the BEOL stacks to ensure device reliability. To enhance the IC performance for new technologies, inter-level dielectric (ILD) made of SiO2 is replaced by low-k and ultra low-k (ULK) dielectrics, which possess a low dielectric constant but have poor mechanical strength. Therefore, the challenge in maintaining BEOL film stack integrity and reliability becomes even greater for advanced technologies. In this paper, we show failure analysis results on a case study of ULK adhesion failure during the IC manufacturing process. The symptoms of the BEOL failure are due to debris dropping on the wafer during chemical mechanical polishing (CMP) after Cu thin film deposition and failure of focusing at wafer extreme edge during the subsequent photolithography process. Extensive mechanical and chemical analyses were conducted on the ULK and adjacent thin films. It was revealed that the interface of ULK and Silicon Nitride from a suspected problematic machine showed abnormally low adhesion energy and high carbon composition. Troubleshooting on that suspected machine found a clog in the foreline. Based on the failure analysis and machine troubleshooting results, the failure mechanism of the case was discussed.

Inclusion of cerium (Ce) oxide particles as an abrasive into chemical mechanical planarization (CMP) slurries has become popular for wafer fabs below the 45nm technology node due to better polishing quality and improved CMP selectivity. Transmission electron microscopy (TEM) has difficulties finding and identifying Ce-oxide residuals due to the limited region of analysis unless dedicated efforts to search for them are employed. This article presents a case study that proved the concept in which physical evidence of Ce-rich particles was directly identified by analytical TEM during a CMP tool qualification in the early stage of 20nm node technology development. This justifies the need to setup in-fab monitoring for trace amounts of CMP residuals in Si-based wafer foundries. The fact that Cr resided right above the Ce-O particle cluster, further proved that the Ce-O particles were from the wafer and not introduced during the sample preparation.

We compare different dc current-based integrated capacitance measurement techniques in terms of their applicability to modern CMOS technologies. The winning approach uses quadrature detection to measure mutual Front-End-Of-Line (FEOL) and Back-End-Of-Line (BEOL) capacitances. We describe our implementation of this approach, Quadrature-clocked Voltage-dependent Capacitance Measurements (QVCM), and its application to 45 nm node BEOL: wire capacitance variability measurements for analog design, and capacitive test structure to measure the effect of metal pattern density on Chemical-Mechanical Polishing (CMP) and Reactive Ion Etching (RIE).

Modern day VLSI Semiconductor devices are manufactured using a chemical mechanical polish (CMP) process. The resultant layers are planar with respect to one another and should be easy to remove. All that needs to be done is to lap the layer until the region of interest is exposed. In practice this has been difficult. This article describes the combination of processes that are required to take full advantage of the strength of deprocessing techniques (lapping, plasma and gel controlled wet chemical deprocessing) to deliver a perfectly planar sample for inspection. A discussion on the thought process required to adequately select the proper chemicals for the gel controlled etch is given. Finally, a typical deprocessing flow is described. It is concluded that this combined solution enables planarity to be maintained across 100% of the device surface. There is less chance the failure site is damaged by the deprocessing.

Challenges in sample preparation for semiconductor failure analysis are always increasing as more complex material and smaller dimensions are required to meet the needs of the semiconductor industry. These changes require the constant need for more refined procedures in all areas of sample preparation, including mechanical polish. This paper presents a newly modified technique which increases the planarity at the critical edge of the sample and results in a larger planar region of interest. The novel method combines both a blocked reactive ion etching and a standard planar polish. It has proven to be a successful delayering technique and helpful in facilitating further analysis. This method has been verified on dies, wafer pieces, and dies thinned and attached to blank silicon for support. It is useful for increasing overall planarity and particularly helpful for the extreme edge.

Scanning capacitance microscopy (SCM) is a powerful technique that may readily be applied to semiconductor failure analysis yielding information on problems stemming from doping issues. This paper details the study of a current leakage failure and outlines the use of the SCM technique for shallow trench isolation applications. A two-step sample preparation technique involving firstly, Chemical Mechanical Polishing (CMP) followed by a wet etch, could improve the sample surface planarization allowing SCM inspection of the STI region.

The semiconductor industry’s efforts to integrate dielectrics into Si devices has driven characterization efforts to address the challenges presented by adoption of this new class of materials. Abundant literature exists on the considerations required for CMP process recommendations for successful fabrication, adhesion requirements for both fabrication and assembly, and considerations for interconnect structure to enable wire-bonding. There is also interest in understanding the wafer level test challenges presented by the low-K devices. In addition to the typical concerns about reaching the best compromise of good contact resistance (CRES) performance with a minimum amount of probe damage, low-K materials present an increased risk of compromising the dielectric or barrier layers beneath bond pads. For a better understanding of the dynamic contact phenomenon of probing and its effect on the integrated circuit (IC) metal stack, a specialized in-situ nanomanipulator tool was developed for simultaneous visualization of probing events with data recording of electrical and load measurements. This paper describes initial research with this new tool.

Smaller technologies and increasing chip functionality has resulted in tightly packed devices and more stacked metal layers. For technologies between 0.25µm and 0.14 µm, stacking packed metal layers required the combination of Tungsten plugs as interconnection and the utilization of Chemical Mechanical Polishing (CMP). “Pillar”, however, is a small metal line, which allows interlevel connections between Tungsten plugs. The size and shape of the pillar can be a yield limiting issue. The process of identification and resolution of the missing metal pillar included yield analysis, electrical and physical failure analysis, root cause analysis and the engineering coordination of photo engineering, etch process engineering, CMP engineering, integration engineering, and inline inspection. Resolving the missing pillar issue has proven to have significant contribution to yield.

The limitation of Focused Ion Beam (FIB) and all charged beam technologies are their insensitivity to the internal composition of materials relative to surface composition. For the most part, charged particle technology cannot provide the resolution at a depth necessary for locating traces either buried under passivation or through silicon. Before CMP planarization was utilized in the industry, it was possible to correlate passivation topography with buried metal traces and manually navigate to the correct x-y coordinates necessary for edit placement. There was still a level of difficulty and CAD navigation helped immensely. With the advent of CMP-planarized metallization, CAD navigation became a necessity, yet still required passivation topography for precise alignment. Current manufacturing processes now planarize all layers, including the passivation, increasing the overall difficulty of navigation. Techniques of drilling “seeker” holes or surface demarcation using FIB and lasers to establish reference fiducials are used extensively [1,2]. Seeker holes and optical-to-FIB image correlation have been useful workarounds for the navigation-related problems presented by advanced ICs. In this paper we will discuss the advantages of Real-Time Optical Imaging coaxially integrated into the FIB, providing non-invasive navigation to nodes for front side and backside applications.

We evaluated laser ablation and sandblasting as preparation methods for package related failures and for backside analysis of ICs. With laser ablation we uncovered gold wedges on an internal board of a PLFBGA package without damage of the gold wires and the board metallization. This was possible by optimization of the laser pulse energy and the pulse repetition rate and by limitation of the ablation area. Sandblasting showed to be a gentle way for backside thinning down to 60 μm silicon thickness. For a surface smoothness sufficient for IR imaging a subsequent planarization treatment is necessary.

New layout overlay technique has been developed based on standard image correlation techniques to support failure analysis in modern microelectronic devices, which are critical to analyze because they are realized in new technologies using sub-ìm design rules, chemical mechanical polishing techniques (CMP) and autorouted design techniques. As the new technique is realized as an extension of a standard CAD-navigation software and as it makes use of standard image format "TIFF" for data input, which is available at all modern equipments for failure analysis, these technique can be applied to all modern failure analysis methods. Here examples are given for three areas of application: circuit modification using Focused Ion Beam (FIB), support of preparation for backside inspection and fault localization using emission microscopy.