Abstract This paper presents the results of an investigation to gain a better understanding of the impact of wafer substrate copper (Cu) contamination on FinFET devices. A chip from a wafer free of Cu contamination and several chips near a Cu contaminated wafer edge were sampled for chemical, structural, and morphological analysis and electrical device performance testing. The contaminated wafer was also annealed at high temperature, trying to drive Cu diffusion further into the Si substrate. TEM analysis revealed that the Cu interacted with Si to form a stable η-Cu 3 Si intermetallic compound. SIMS analysis from the backside of the wafer detected no Cu even after most of the backside material was removed. Likewise, electrical nanoprobing showed no parametric drift in the FinFETs near the edge of the wafer, comparable to device behavior in a Cu-free Si substrate. These results indicate that the formation of η-Cu 3 Si with a well-defined crystalline structure and stable stoichiometry immobilizes Cu diffusion in the Si substrate. In other words, the impact of Cu diffusion in silicon has no effect on device performance as long as η-Cu 3 Si does not form in the FinFET channel or short any structures within the chip.

Abstract The examination of partially deprocessed ICs for well imaging has been investigated. First it has been shown [1] that Ga+ FIB imaging can readily and strongly highlight the N-well / P-well boundary in an IC as shown again here. Second, a model which only considers secondary electron creation and scattering [2] is confirmed to be sufficient for understanding these imaging effects. Heavy Ga doping provides no marked change in PVC (passive voltage contrast). Then comparisons in the same field of view between optimized He+ and Ga+ imaging, has shown that He+ provides much greater PVC contrast when looking through deep oxide, and much better resolution on shallow surfaces. The quantitative model Stopping and Range of Ions in Matter (SRIM) [3] was consulted and confirmed these expectations for resolution and depth superiority of the He+ beam. According to the SRIM, there may even be less damage from the He+ beam. Yet these known effects of Ga+ damage has not prevented its widespread use in semiconductor FA and process monitoring. Thus, the use of GFIS (Gas field ion source) He+ beam for voltage contrast and junction imaging warrants further exploration.

Abstract Focused Ion Beam (FIB) circuit edit allows for rapid prototyping of potential semiconductor design changes without the need to run a full manufacturing cycle in a semiconductor Fab. By FIB editing a completed module, thorough testing on the bench or in a full system can be achieved. Logic can be toggled, validation of speed enhancements performed, and constructive and destructive failure analysis can be enabled. In order to fulfill all the needs of clients in a rapidly evolving SOC driven market, simply modifying existing devices by “rewiring” circuits is becoming insufficient. Often the team is tasked with making very repeatable structures to aid the circuit analysis group. These include relatively precise resistors for tuning RF circuits (part of an RC network), adding known loads or delays, et cetera. Naturally resistive FIB deposited metal lines connected to the existing circuitry can be used in this capacity. FIB chip edit is considered to be a “Direct Write” process. The beam pattern in conjunction with process gases defines the regions of milling and deposition. Unfortunately, FIB edit is rarely an exact science. In many cases, a number of characteristics seem to be outside the realm of precise repeatable control. This is evident not only in individual tool operational logs but also in FIB tool matching, where maintaining identical system performance within the lab is difficult or nearly impossible. These characteristics are highly dependent on precursor reservoir composition and flow, surface adsorption conditions, beam patterning integrity, and the total interaction space of competing back sputtering during the new material structure formation. Due to these factors, the shape, composition and electrical performance of metal and insulator depositions vary over an often unacceptable range. As a result, we were not meeting the needs of some critical customer applications. Direct written precision resistive structures displayed several issues for which iterative edits were required to compensate for variability. When attempting to create an exact resistance, this process was not reliable, nor was it repeatable enough for accurate circuit performance trimming. Space-constrained serpentine resistors or multiple discrete resistors side-by-side showed the greatest process variability. Metal deposition processes tend to be somewhat self-limiting, so thick boxprofile lines are difficult to form. Conductive material deposited outside of the pattern definition (overspray) results in line-to-line leakages. Attempts to remove the overspray thru ion beam assisted etch-back tends to damage the deposited conductors and underlying insulators. The low-k region between lines can become cross-linked, experience gallium doping, and become tungsten impregnated. This lowered the resistivity of the insulator, increased the resistivity of the conductor, and produced variability in the device which was especially an issue when dealing with varying initial substrates. GLOBALFOUNDRIES began a project to create a more robust repeatable resistive structure by removing several variables. Rather than direct writing lines onto a top surface layer, a confined deposition based on the concepts of dual damascene processing used with copper layers in modern semiconductor fabrication will be employed. The damascene process begins with the definition of a box to be filled with a conductive material. The process of ion beam gas assisted anisotropic etching/milling has a far more predictable outcome than ion beam induced deposition. It is possible to create a surface box mill or even a deep drilled via of desired dimensions with a more consistent repeatability. Deposition of tungsten into a confined region using, for example, a W(CO)6 precursor and a Ga+ ion beam results in an excellent via fill. Using this behavior, precision resistors can be created with metal deposition within the trenches which are created by the gas assisted mill. An enclosed space can be filled nearly void-free, and has repeatable electrical parameters. The self-limiting factors with tungsten deposition go away as sputtered material becomes trapped within the well resulting in a near limitless Zheight potential. The constant dielectric with a uniform and contained tungsten fill can allow for a well-defined resistivity for the FIB deposited tungsten material. Having a known resistivity, calculation of dimensions for resistive and inductive structures during the design process becomes feasible. With process variability under control, structures can be formed reliably enough to offer this as a service to customers.

Abstract An application-specific integrated circuit (ASIC) for a high reliability application is found to have a missing sidewall spacer in a single transistor. Manufacturer burn-in and standard component electrical tests do not capture this defect. The defect manifests after exposure to ionizing radiation. Photon emission microscopy (PEM), laser voltage imaging (LVI), and laserassisted device alteration (LADA) are used to isolate the failure site. At the failure site a focused ion beam (FIB) cross section indicates that a doubly doped drain (DDD) (N+) is likely present where a lightly doped drain (LDD) is designated. This defect leads to a failure mode that is consistent with hot-carrier injection in complementary metal-oxide semiconductor (CMOS) transistors. This paper presents the testability from a fault isolation aspect, shmoo plot characterization, and backside optical techniques to identify its spatial location. A discussion of the results includes why ionizing radiation allowed the defect’s capture and potential implications of using ionizing radiation as a viable failure analysis technique.

Abstract In 1986 the Atomic Force Microscope (AFM) was invented by Gerd Binnig, Christoph Gerber, and Calvin Quate [1]. Since then, numerous analytical techniques have been developed and implemented on the AFM platform, evolving into what is collectively called the Scanning Probe Microscope (SPM). The SPM has since become well established as a mainstream analytical instrument with a continually increasing role in the development of nanoscale semiconductor technologies providing critical data from initial concept to technology development to manufacturing to failure analysis [2]. Scanning Capacitance Microscopy (SCM) has a longstanding, well-established track record for detecting dopant-related mechanisms that adversely affect device performance on planar (Field Effect Transistor) FETs as well as other structures (e.g., diodes, capacitors, resistors). The semiconductor industry’s transition to three dimensional FinFET devices has resulted in many challenges with regard to device analysis. This is especially true when it is necessary to perform detailed dopant analysis on a specific device; the device may be comprised of a single or multiple fins that have been called out specifically through traditional fault localization techniques. Scanning Capacitance Spectroscopy (SCS) is an analytical method, implemented on the SCM platform in which a series of DC bias conditions is applied to the sample and the carrier response is recorded using SCM [3]. SCS has a proven history of highlighting dopant related anomalies in semiconductor devices, which, in some instances, might not otherwise be “visible”. This paper describes successful application of SCM and SCS in showing, in full detail, a dopant-related failure mechanism on an individual, location-specific 14 nm FinFET.

Abstract Two-dimensional semiconductors such as atomically-thin MoS2 have recently gained much attention because of their superior material properties fascinating for the future electronic device applications. Here we investigate the nanoscale dominant carrier distribution on atomically-thin natural and Nbdoped MoS2 mechanically exfoliated on SiO2/Si substrates by using scanning nonlinear dielectric microscopy. We show that a few-layer natural MoS2 sample is an n-type semiconductor, as expected, but Nb-doped MoS2, normally considered as a p-type semiconductor, can unexpectedly become an n-type semiconductor due to strong unintentional electron doping.

Abstract Threshold Voltage (Vt) of MOSFET controls transistor’s on and off state. Vt is usually depends on gate oxide thickness and operating temperature. Systematic failure analysis for a Vt shift issue, should also consider the channel doping which affects the inversion layer formation. In this article, the failure case of a shift in the Vt of a Power MOSFET V is studied. Secondary Ion Mass Spectrometry (SIMS) is found to be the most direct way for detecting any abnormality in the channel doping profiles. A comprehensive simulation is performed showing that the Phosphorus level diffusion from substrate was so high that it affects the doping concentration of channel.

Abstract Threshold voltage (Vt) shift was measured, using atomic force probing (AFP) technique, in the pullup PFETs of high density SRAM bitcell arrays in 90nm CMOS bulk technology. This shift caused catastrophic yield loss. The direct measurements of dopant distribution both in plan view and x-section using Scanning Capacitance Microscopy (SCM) technique suggested counter doping of the P-poly had occurred. A single mask modification was shown to validate the observation and eliminated the counter doping resulting in drastic yield enhancement to about 60% from nearly no yield.

Abstract Currently many methods are available to obtain a junction profile of semiconductor devices, but the conventional methods have drawbacks, and they could be obstacles for junction profile analysis. This paper introduces an anodic wet etching-based two-dimensional junction profiling method, which is practical, efficient, and reliable for failure analysis and electrical characteristics evaluation.

Abstract Failures caused by threshold voltage (Vt) shifts in sub-100nm technology transistors have become very difficult to both analyze and determine the failure mechanism. The failure mechanisms for Vt shifts are typically non-visible for traditional physical analysis methods such as SEM inspection or traditional TEM analysis. This paper demonstrates how nano-probing was used to carefully and fully characterize the Vt shift failure to determine a specific electrical signature for a specific failure mechanism and then with junction stain Transmission Electronic Microscopy (TEM) verify the subtle doping defect affecting the Static Random Access Memory function in the 65nm generation node. Device failure due to a lack of Lightly Dope Drain (LDD) implant induced by an inconspicuous spacer defect was determined to be the root cause of the failure.

Abstract The techniques of doping profile inspection, such as SEM (Scanning Electron Microscope) dopant contrast, SEM wet stain and SCM (Scanning Capacitance Microscope) have been widely used in failure analysis for implant root causes identification. The applications of real FA (Failure analysis) cases and advantages/disadvantages will be discussed and demonstrated in this paper. To sum up, SEM dopant contrast is the most convenient method for doping profile inspection, and SCM is the best method for low doping profile observation.

Abstract The Voltage Contrast (VC) [1-3] and Dopant Contrast [4-7] in Scanning Electron Microscopy (SEM) [8] have been widely used in the Silicon (Si) semiconductor manufacturing field to localize the failure site from plane-view and inspect the doping profile along cross-section with spatial resolution in the nanometer (nm) range. In this article, we demonstrate how the surface effect, such as topography or material variation, impacts the conventional prediction for the voltage and dopant contrast in the SEM images. The mechanisms and applications for the SRAM and real products are described.

Abstract The sample preparation required for a typical backside circuit edit (CE) is a significant barrier for some labs, as it requires specific hardware and considerable operator expertise. There are also instances in which it is not possible to mechanically thin the silicon in the typical fashion. This paper addresses the possibility of backside CE be performed on full-thickness silicon devices and the possibility of skipping off the thinning step, as well as the advantages and disadvantages of this approach. Sample trenches are shown, and trenching optimization experiments are described. The paper addresses the issues of navigation, including IR imaging through full-thickness silicon, and how it depends on the sample doping levels. Finally, it presents data on a novel navigational technique that can be employed to improve targeting accuracy. The paper shows that backside CE on full-thickness silicon devices is possible despite the challenges.

Abstract MOSFET devices are routinely measured at the probe pad level with conventional capacitance-voltage (CV) measurement instruments. Such measurements are done at the front end of line (FEOL) and back end of line (BEOL) process completion levels. The CV data is used to monitor the process and verify certain parametrics such as effective oxide thickness (EOT), Tox, gate drain overlap capacitance (Miller capacitance), trapped charge, diffusion/halo implant oxide leakage, doping concentration, threshold implant level and many others. This type of testing is treated at length in the classic text of Nichollian and Brews [1]. The introduction of Nanoprobe Capacitance Voltage Spectroscopy (NCVS) of discrete MOSFET devices and the method of performing scanning capacitance imaging (SCM) have been previously presented [2]. In that work, the authors used a capacitance sensor to measure the capacitance of an individual failing embedded DRAM capacitor. This paper will describe nanoprobe CV measurements of a discrete finger device from a multiple finger test structure and show comparable results obtained at the probe pad level, using an improved version of the earlier capacitance sensor. By comparing the BEOL test structure measurements with NCVS results from a single finger, we will verify and calibrate the nanoprobing technique.

Abstract Doping profile measurements in extremely small features like transistor gates or source/drain regions is a challenging task for the semiconductor industry. In our article, we successfully used an atom probe tomography (APT) tool to measure the doping concentration and profile of the dopant elements in a commercial 65 nm product. APT not only delivers doping concentrations but also gives the highest spatial resolution (sub-1 nm) three-dimensional compositional information of any microscopy technique.

Abstract Scanning capacitance microscopy (SCM) is an SPM technique which measures capacitance variation between tip and sample generated by applied AC bias while the tip is scanning in contact mode. Focused ion beam (FIB) milling is the more precise method to perform cross-sectioning of a specific site. The surface amorphization and charge trap layers formed during FIB machining affect the SCM dC/dV signal. This article demonstrates that micro-cleaving and FIB milling are capable of preparing a cross-sectional sample for 2D doping profiling of a specific site for SCM observation. Using the Micro-cleaving technique, a cross-sectional sample can be prepared easily with higher accuracy and shorter time than using a polishing method. However, Micro-cleaving can't be used by itself in the case of cross-sectioning a pattern formed by front end processing of sub-micron patterns. The FIB technique can assist the Micro-cleaving technique in cleaving of front end patterns.

Abstract This paper discusses the failure analysis process of a DC failure using an in-FIB (Focused Ion Beam) nanoprobing technique with four probes and a scanning capacitance microscope (SCM) in advanced DRAM devices. Current-Voltage (I-V) curves measured by the nanoprobing technique indicate the curve of the failed device is different from that of the normal device. The failed device causes a high leakage current in the test. The cross-sectional 2-D doping profile of SCM verifies the region of the P-Well has shifted to create a leakage path that causes this failure.

Abstract The usefulness of scattering-type near-field optical microscopy for mapping the material and doping in microelectronic devices at nanoscale resolution is demonstrated. Both amplitude and phase of infrared (λ = 10.7 μm) laser light scattered by a metallised, vibrating AFM tip scanned a few nanometers above the sample are detected and transformed into images showing contrast of materials, as well as of doping concentration. Cross-sections through layers as thin as 20 nm have been clearly imaged.

Abstract In the field of failure analysis, electrical failures caused by improper implantation are often difficult to debug especially for fully processed products. Familiar implantation failure issues include improper implantation concentration, error doping types, incorrect doping ranges, and etc. Although some FA equipments, such as secondary ion mass spectrometry (SIMS), spreading resistance probe (SRP) and scanning capacitance microscope (SCM) [1] [2] [3], can do detail or quantitative analysis for these failure issues, most of these FA jobs are time-consuming and have a detection limitation at the size of failure area. This limitation may restrict the FA applications because the failure area is usually small at the fully processed products after fault isolation. In this paper, two examples with improper doping type and concentration will be analyzed by using a newly developed FA method. Instead of using traditional cross-section (X-S) stain method, we utilize a plane-view stain method to compare the doping type and doping concentration between normal and failed regions. With the aid of the plane-view stain method, we can have a quick check at the suspected failure area with improper front-end implantation before specific SCM analysis.

Abstract This article describes a 90nm technology SRAM soft fail analysis. The bitmaps of affected wafers show a large number of wafer edge dies failing with single cell cluster fails at supply voltages below 1.0V. The fails appear in characteristic areas within a 256k dualport SRAM memory block. Nanoprobing was used for electrical localization at the cell level by means of a Multiprobe atomic force probe (AFP) system. Fail areas exhibit very weak PFET drain currents several orders of magnitude below the target values, while the drain currents of NFET cell transistors are in the expected range. For fail visualization a junction stain was applied to TEM samples to delineate areas with different doping levels. Due to differences in etch behavior between failed and reference areas, missing LDD extensions and a partially blocked source/drain (S/D) implantation were identified as the root cause of the fails.