Photoresist (PR) profiles tend to have deformation and shrinkage with typical transmission electron microscopy (TEM) sample preparation methods using a focused ion beam scanning electron microscope (FIB-SEM). As the temperature increases during the TEM sample preparation, it may lead to deformation and shrinkage in PR profiles. In this study, we analyze the impact when performing the sample preparation at a cold temperature using a cryo-FIB to minimize deformation and shrinkage issues. To test this methodology, the TEM sample preparation process was performed under different conditions. From these experiments, the TEM results with full cryo conditions showed that the PR line to space ratio was closest to the target, which is the sample’s real line to space ratio (1:1), and the bottom anti-reflective coating (BARC) shrinkage was minimized.

Rapid identification of organic contamination in the semi and semi related industry is a major concern for research and manufacturing. Organic contamination can affect a system or subsystem’s performance and cause premature failure of the product. As an example, in February 2019 the Taiwan Semiconductor Manufacturing Company (TMSC), a major semiconductor manufacturer, reported that a photoresist it used included a specific element which was abnormally treated, creating a foreign polymer in the photoresist resulting in an estimated loss of $550M [1].

Abnormal inline defects were caught after nitride spacer etching processes. Detailed MEBES layout checking and inline SEM inspection revealed that such defects always appeared at the boundaries in between PFETs and NFETs regions. The microstructure and chemical composition of the defects were analyzed in detail by various TEM imaging and microanalysis techniques. The results indicated that the defect possessed core-shell structure, with oxide core and nitride shell. Based on the TEM failure analysis results and manufacturing processes, we conclude that the defects originated from PR fencing due to the PR hardening during PFET and NFET LDD/Halo implantation. The oxide core was generated during oxide spacer formation using an ozone-TEOS process, which was responsible for the nitride spacer under-etch issue.

This paper presents the results of a study on yield loss in wafers produced using a 0.25-μm CMOS process. It describes how the authors determined that a short in the M1 metal layer was the major yield killer and how they traced the cause to excess Cu that they believe migrated to the bottom of the Al(Cu)/TiN interface, forming θ-phase Al2Cu precipitates known to interfere with metal etching processes. It explains how TiN bridges, the result of incomplete etching, were observed between adjacent metal lines in failed die, confirming the authors’ theory and shedding light on potential solutions to the yield problem.

A case history is presented for the failure analysis of a 0.5u CMOS A/D converter in which high fallout occurred after autoclave stressing. The observed failure mode of degraded signal-to-noise distortion (SINAD) ratio (measured in dB) was found to affect devices within a specific bandwidth centered around 5MHz. From a circuit designer’s viewpoint, an explanation for this unique failure mode did not readily present itself. Yet, using straightforward failure analysis techniques, involving laser ablation of photoresist and selective etching of passivation, the specific failing circuit block was isolated. Crosssectional analysis, scanning electron microscopy (SEM), and energy dispersive spectroscopy (EDS) found evidence of residual photoresist at topography related voids in the nitride passivation layer. The photoresist reacts with moisture in the autoclave, resulting in increased capacitance at minimum-spaced top layer metal lines. This failure mechanism correlates with the observed maximum SINAD degradation around 5MHz: at this frequency the signals along the affected metal lines are at their maximum voltage swing. This failure mechanism is potentially an issue for any similar high-speed, high-resolution designs.

Electrical data from chromium-silicon-carbon (CrSiC) thin film resistors (tfr) consistently showed highly variable contact resistance (Rc) to the aluminum (Al) interconnect. Transmission electron microscopy data from CrSiC/Al interfaces exhibiting high Rc showed a conformal, amorphous layer sandwiched between the tfr and Al. Auger data from the tfr/Al interface showed this ‘crud’ layer to contain increased C, S, and SiOx. Auger data from CrSiC films on test wafers exposed to the process steps before Al deposition showed additional growth of the ‘crud’ layer after each photoresist (PR) operation. In addition, Rc variability was reduced on product wafers from split lots when 2x the normal PR strip time was used compared to the normal strip time. A Designed Experiment (DOE) to examine improving the removal of this ‘crud’ layer was run on product lots utilizing two factors: the standard strip and a two-step strip. Electrical results for both Rc and die yield were significantly improved using the two-step process. The variability of the Rc was also reduced.