Photoresist (PR) profiles tend to have deformation and shrinkage with typical transmission electron microscopy (TEM) sample preparation methods using a focused ion beam scanning electron microscope (FIB-SEM). As the temperature increases during the TEM sample preparation, it may lead to deformation and shrinkage in PR profiles. In this study, we analyze the impact when performing the sample preparation at a cold temperature using a cryo-FIB to minimize deformation and shrinkage issues. To test this methodology, the TEM sample preparation process was performed under different conditions. From these experiments, the TEM results with full cryo conditions showed that the PR line to space ratio was closest to the target, which is the sample’s real line to space ratio (1:1), and the bottom anti-reflective coating (BARC) shrinkage was minimized.

Rapid identification of organic contamination in the semi and semi related industry is a major concern for research and manufacturing. Organic contamination can affect a system or subsystem’s performance and cause premature failure of the product. As an example, in February 2019 the Taiwan Semiconductor Manufacturing Company (TMSC), a major semiconductor manufacturer, reported that a photoresist it used included a specific element which was abnormally treated, creating a foreign polymer in the photoresist resulting in an estimated loss of $550M [1].

Through inline processing of a prospective Spin on Hardmask (SOH) material, bubble defects were observed randomly across a wafer. Several complementary FA techniques were utilized to characterize the bubble defects including SEM, TEM, and chemical analysis techniques. The root cause of defect formation was identified as a raw material imperfection in SOH, which led to excessive outgassing. Imperfections within the substrate formed nucleation sites for outgassing of SOH material forming bubbles, which allowed voids to propagate. These findings led to implementation of greater quality control methods by the raw material manufacturer.

The back-end-of-line (BEOL) structure of current IC devices fabricated for advanced technologies is composed of film stacks with multiple interfaces. The requirement of high interfacial strength is therefore necessary between the different layers in the BEOL stacks to ensure device reliability. To enhance the IC performance for new technologies, inter-level dielectric (ILD) made of SiO2 is replaced by low-k and ultra low-k (ULK) dielectrics, which possess a low dielectric constant but have poor mechanical strength. Therefore, the challenge in maintaining BEOL film stack integrity and reliability becomes even greater for advanced technologies. In this paper, we show failure analysis results on a case study of ULK adhesion failure during the IC manufacturing process. The symptoms of the BEOL failure are due to debris dropping on the wafer during chemical mechanical polishing (CMP) after Cu thin film deposition and failure of focusing at wafer extreme edge during the subsequent photolithography process. Extensive mechanical and chemical analyses were conducted on the ULK and adjacent thin films. It was revealed that the interface of ULK and Silicon Nitride from a suspected problematic machine showed abnormally low adhesion energy and high carbon composition. Troubleshooting on that suspected machine found a clog in the foreline. Based on the failure analysis and machine troubleshooting results, the failure mechanism of the case was discussed.

Abnormal inline defects were caught after nitride spacer etching processes. Detailed MEBES layout checking and inline SEM inspection revealed that such defects always appeared at the boundaries in between PFETs and NFETs regions. The microstructure and chemical composition of the defects were analyzed in detail by various TEM imaging and microanalysis techniques. The results indicated that the defect possessed core-shell structure, with oxide core and nitride shell. Based on the TEM failure analysis results and manufacturing processes, we conclude that the defects originated from PR fencing due to the PR hardening during PFET and NFET LDD/Halo implantation. The oxide core was generated during oxide spacer formation using an ozone-TEOS process, which was responsible for the nitride spacer under-etch issue.

We investigated the swelling behavior of dry film photoresist in rinse process after development by varying the hardness of water. We inspected the appearance of sidewalls and the foot of the resist. We also measured the depth of once swollen resist using a FIB (focused ion beam) and analyzed the chemistry of the resist after rinse using an XPS (X-ray photoelectron spectroscopy). We experimentally proved that divalent cations such as Ca2+ and Mg2+ in hard water could be exchanged with Na+ on the resist surface and quench swelling of the exposed resist in rinse. This study indicates that the use of hard water in rinse process may result in better line definition and resolution in PCB (printed circuit board).

A system-on-chip processor (90 nm technology node) was experiencing a high basic function failure rate. Using a lab-based production tester, laser assisted device alteration, nanoprobing, and physical inspection; the cause of failure was traced to a single faulty P channel transistor. The transistor had been partially subjected to N doping due to poor photo-resist coverage caused by halation.

Inherently small process margins in patterning are a dominant cause of device yield variability, when process conditions or production lines change. This paper highlights the fact that in spite of a perfect lithographic model, the post OPC variation can be substantial due to manufacturing variability. Pattern integrity is a non-intuitive complex mix of manufacturing process practices combined with manufacturable design practices. Failure analysis is the only effective means for filling the understanding gap for yield management in this case. A case study of yield drop due to layout dependent process marginality and a methodical approach to get to the root of the problem are described in this paper.

SEM analysis of 193-nm photoresist profiles after cross section is seen to be critical because of the shrinkage of the photoresist material during electron beam exposure. With a combination of AFM and SEM investigations on AuPd sputter prepared samples an averaged shrinkage behaviour of height and width of resist lines of varying geometry can be quantitatively determined. This helps to a more accurate determination of resist line profiles.

We report on a quantitative investigation of doping-induced contrast and topography-induced contrast in photoelectron emission microscopy (PEEM). Calibration samples were fabricated using standard photolithography and focused ion beam writing to test both types of contrast. Using a near-threshold light source, we find that the doping-induced contrast increases monotonically with B concentration over the measured range of 10 17 – 2x10 20 cm -3 . The variation in doping-induced contrast as incident photon energy is varied was also investigated. Optimal doping-induced contrast and PEEM sensitivity is achieved by imaging with photon energy slightly above the highest nominal photothreshold of interest. The photoemission model, based on near-threshold emission, used to describe doping-induce contrast gives good agreement with the measured intensities. Thus, measuring the relative intensity ratio provides a robust technique for determining doping levels. Topography-induced contrast was investigated by imaging Ti samples of various step heights (75, 150, 290, and 550 nm). Image data suggests that edge contrast increases with step height. Numerical simulations show that non-uniform electrostatic fields at step edge are responsible for this contrast. Experimentally, we systematically vary the lateral field strength and show that edge contrast can be controlled. This technique could be useful in failure analysis by identifying breaks in metal lines.

This paper presents the results of a study on yield loss in wafers produced using a 0.25-μm CMOS process. It describes how the authors determined that a short in the M1 metal layer was the major yield killer and how they traced the cause to excess Cu that they believe migrated to the bottom of the Al(Cu)/TiN interface, forming θ-phase Al2Cu precipitates known to interfere with metal etching processes. It explains how TiN bridges, the result of incomplete etching, were observed between adjacent metal lines in failed die, confirming the authors’ theory and shedding light on potential solutions to the yield problem.

The migration of microprocessor packaging from wire bond to flipchip technology in silicon "microsurgery" posed some challenges to on-chip circuit edit. The physical debug process through the backside silicon substrate was proposed as the common solution. The focus of this article is on step 2 of this process, namely the milling of large trenches over the edit area. Laser Chemical Etcher (LCE) was commonly used for this task. This article presents an alternative technique based on plasma dry etch process which consists of three steps: photolithography, plasma etching, and acoustic polishing. A detailed description of each step is provided, along with the details of experiments that were conducted for process optimization. The technique was successfully demonstrated in the preparation for backside FIB editing. However, the success rate of the proposed method is still lower than the LCE but this method can serve as a reliable backup process for the LCE.

A case history is presented for the failure analysis of a 0.5u CMOS A/D converter in which high fallout occurred after autoclave stressing. The observed failure mode of degraded signal-to-noise distortion (SINAD) ratio (measured in dB) was found to affect devices within a specific bandwidth centered around 5MHz. From a circuit designer’s viewpoint, an explanation for this unique failure mode did not readily present itself. Yet, using straightforward failure analysis techniques, involving laser ablation of photoresist and selective etching of passivation, the specific failing circuit block was isolated. Crosssectional analysis, scanning electron microscopy (SEM), and energy dispersive spectroscopy (EDS) found evidence of residual photoresist at topography related voids in the nitride passivation layer. The photoresist reacts with moisture in the autoclave, resulting in increased capacitance at minimum-spaced top layer metal lines. This failure mechanism correlates with the observed maximum SINAD degradation around 5MHz: at this frequency the signals along the affected metal lines are at their maximum voltage swing. This failure mechanism is potentially an issue for any similar high-speed, high-resolution designs.

Electrical data from chromium-silicon-carbon (CrSiC) thin film resistors (tfr) consistently showed highly variable contact resistance (Rc) to the aluminum (Al) interconnect. Transmission electron microscopy data from CrSiC/Al interfaces exhibiting high Rc showed a conformal, amorphous layer sandwiched between the tfr and Al. Auger data from the tfr/Al interface showed this ‘crud’ layer to contain increased C, S, and SiOx. Auger data from CrSiC films on test wafers exposed to the process steps before Al deposition showed additional growth of the ‘crud’ layer after each photoresist (PR) operation. In addition, Rc variability was reduced on product wafers from split lots when 2x the normal PR strip time was used compared to the normal strip time. A Designed Experiment (DOE) to examine improving the removal of this ‘crud’ layer was run on product lots utilizing two factors: the standard strip and a two-step strip. Electrical results for both Rc and die yield were significantly improved using the two-step process. The variability of the Rc was also reduced.

This article analyzes the cause of Vcc shorts in advanced microprocessors. In one instance, an advanced microprocessor exhibited Vcc shorts at wafer sort in a unique pattern. The poly silicon was narrow in one section of the die. The gates were shown to measure small, but no electrical proof of the short could be seen. To prove the short existed as a result of the narrow gate, a Scanning Capacitance Microscope (SCM) was utilized to confirm electrical models, which indicated a narrow poly silicon gate would result in Vcc shorts. High frequency dry etching and UV-ozone oxidation were employed for deprocessing. The use of the SCM confirmed the proof that the Vcc shorts were caused by narrow gate length which causes its leaky behavior. This conclusion could have only been confirmed by processing of material through the wafer foundry at the cost of money and time.

Silicon planar phototransistors in hermetic pig-tail metallic package for airborne system application failed the acceptance test because of low responsivity. No significant difference between the electrical characteristics of good and defective devices could be detected by systematic investigation of focusing lens, anti-reflecting coating, optical alignment, and by internal electrical microprobing. EBIC inspection instead revealed that all defective phototransistors were affected by an anomalous region with a very high photo-carrier generation rate. This effect was produced by the misalignment of the emitter metallization which partially exposed the emitter-base junction. Partial exposition of the emitter diffusion to impinging radiation generates an induced photocurrent in the emitter-base junction which has opposite direction with respect to the photocurrent induced in the base-collector junction. The extra photocurrent in the base-emitter junction reduces the emitter-base forward polarization and, as direct consequence, the phototransistor responsivity is lower.