Backside decapsulation is necessary to be able to perform failure analysis on devices with dense metallization. However, for down bond devices with the down bonds located too close to the die edge, using the traditional chemical method tends to overetch the bonding wires, and using the precision milling tool is too time-consuming. In this paper, a new inexpensive and efficient method is developed for challenging down bond devices with the die attach pad (DAP) buried in the molding compound. This method uses laser to reduce the thickness of the whole die area molding compound first and then partially expose the DAP, which length and width are smaller than that of die area. Lastly, it uses a chemical method to remove the die DAP, and keep a measured thickness of the molding compound to protect the bonding wires from being over-etched.

Analog Devices Inc. (ADI)’s Radar Receive Path Analog Front End Amplifier (AFE) with a 0.18um 6-metal Fab Process has failures related to Power-Down and Scan test parameters which were endorsed for Failure Analysis. Fault localization is quite challenging because it involves 6 metal layers. This has been resolved with the availability of Synopsis Avalon software with capability to convert the complete Cadence schematics and layout that is usable for Failure Analysis, through cross-mapping with the fault localized area-of-interest (AOI) on the actual reject part with the die schematics and layout, and identifying the failing component and circuit block. This leads to the creation of the failure model related to the reported failure mode and the determination of the appropriate failure mechanism related to fabrication defects between the adjacent metallization layers and defects on between the polysilicon and substrate layer. This helps speed up the FA Cycle Time and achieve an accurate failure mechanism, which later resolves the fab defect issue with the Fab process owner.

Nowadays, semiconductor components are widely used in home electronic appliances, vehicles, industrial motor controls and beyond. The performance and reliability of these components are becoming more crucial and critical. Generally, a semiconductor component consists of lead frames, wires, dies and die attaches. Within the die, the die backside metallization, also known as “BSM,” plays an important role in electronic component manufacturing. The BSM is a layer that promotes good adhesion, electrical properties and long-term stability as a conductive pathway to the circuits. As such, the inspection on BSM is needed to ensure robustness. Several conventional methods have been developed to analyze the die backside metallization. In this paper, we will discuss the inspection on backside metallization and comparison among five sample preparation methods: mechanical cross section with ion milling, mechanical cross section with FIB cleaning, die frontside decapsulation with FIB cut from die surface and FIB cut from die sidewall, and component frontside lapping with FIB from the remaining silicon. Result comparison will be discussed in case studies and the advantages and disadvantages of the five methods will be compared.

This paper presents backside physical failure analysis methods for capturing anomalies and defects in advanced flip-chip packaged, bulk silicon CMOS devices. Sample preparation involves chemically removing all the silicon, including the diffusions, to expose the source/drain contact silicide and the gate of the transistors from the backside. Scanning Electron Microscopy (SEM) is used to form high resolution secondary and/or backscattered electron images of the transistor structures on and beneath the exposed surface. If no visual defects/anomalies are found at the transistor level, the Electron Beam Absorbed Current (EBAC) technique is used to isolate short/open defects in the interconnect metallization layers by landing nano-probe(s) on a transistor’s source/drain silicide or on the gate. Using the combination of secondary and backscattered electron imaging and backside EBAC thus allows defects residing in either the transistors or the metal nets to be found. Case studies from 20 nm technology node graphics processing units (GPU) are presented to demonstrate the effectiveness of this approach.

With the introduction of new packaging technologies and the great variety of semiconductor devices, new decapsulation tools are needed to improve failure analysis with a higher success rate, and to improve quality control with a higher confidence level. Conventional downstream microwave plasma etchers use CF4 or other fluorine containing compounds in the plasma gas that causes unwanted overetching damage to Si3N4 passivation and the Si die, thus limiting its use in IC package decapsulation. The approach of atmospheric pressure O2-only Microwave Induced Plasma (MIP) successfully solves the fluorine overetching problem. Comparison between MIP, conventional plasma, acid etching based on several challenging decapsulation applications has shown the great advantage of MIP in preserving the original status of the die, wire bonds, and failure sites. One of the challenging failure analysis cases is Bond-Over-Active-Circuit (BOAC) devices with exposed thin copper metallization traces on top of Si3N4 passivation. The BOAC critical die structures present a challenge to both conventional plasma and acid decapsulation. The use of MIP to solve the BOAC device decapsulation problem will be discussed in detail through multiple case studies. It appears that the MIP machine is the only approach to decapsulate BOAC devices without causing any damage to the exposed copper on passivation critical structure, which demonstrates the failure analysis capabilities of the MIP system.

This paper presents a case study on photon emission from metals and demonstrates the capability of Emission Microscopy Si-CCD camera to detect micro metal bridges on functional failures of Analog devices.

The physical analysis of sub-100nm device technologies in many cases requires the total or partial removal of the multiple layers of metallization that route electrical signals and power through the device. This paper presents a simple and quick polishing technique that will remove the entire metallization stack above metal 1 for a 55nm technology device, which results in significantly reducing the time needed to reach the transistor level of the device and also greatly improving uniform planarity across the device. This method is intended for those cases in which gaining access to the transistor layer is required for electrical characterization and physical analysis. The improved speed of this polishing technique to reach the transistor layer has greatly reduced cycle time. The results for the polishing method have been relatively reliable with over a 95% success rate.

With the shrinkage of the IC device dimensions, Cu and ultra-low-k dielectric were introduced into IC devices to reduce RC delay. Ultra-low-k dielectrics generally suffer more damage than silicon oxide dielectric during process integration and subsequently cause reliability degradation. Therefore, ultra-low-k damage characterization on Cu damascene structures is of great importance to understand the damage mechanisms. This paper describes the application of UV-Raman microscopy with enhanced spatial resolution and signal sensitivity for characterizing ultra-low-k dielectric in the three-dimension structure of Cu metallization with nanometer feature size. It shows UV-Raman technique has an advantage in analyzing ultra-low-k layer on patterned wafer and extracting ultra-low-k signals from Cu/ultra-low-k mixed structure. UV-Raman is also effective to characterize the ultra-low-k degradation for ultra-low-k related reliability analysis by time dependent dielectric breakdown (TDDB) test.

Focused ion beam (FIB) circuit edit (CE) is an integral part of IC debug, fault-isolation, and low yield analysis. Regarding FIB microsurgery, complexity is growing with the shrinking of dimensions of lower level metallization while the redistribution layer (RDL) structures can increase in all three dimensions. This requires continuous development of CE processes to address these opposite dimension trends and material variations. There are two venues to address CE, accessing from the front side (FS) or from the back side (BS) of an IC. This paper describes the FS techniques and methodologies developed to edit the RDL technology. The goal of this work is to demonstrate on a Cu GND/power plane the performance of the halogen-based contamination process. Results shows that the benefit of reduced time to remove thick Cu metallization is surely advantageous for CE throughput as well as for improving edit success rates.

This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the backside of the device as a means of locating metallization defects on state of the art bulk silicon and SOI based microprocessor technologies. It builds on previous work which focused only on flip-chip SOI samples. This paper will demonstrate additional EBAC techniques and the ability to analyze devices processed in bulk silicon technology. Also included are the results obtained from an SOI device mounted in a non flipchip package type. Additional details related to sample preparation, equipment used, and improved practices are described.

One method of reducing costs in the packaging sector is to switch from gold bond wires to copper. Thicker copper wires (over 2 mils) can be safely decapsulated using a ratio mixture of fuming acids. Some surface etching of the copper will occur, but the wire will remain electrically viable. Microwave Plasma can provide a safer alternative for decapsulating packages with copper bondwires and exposed copper metallization. In this paper, experimental deprocessing of copper bond wire and copper metallization using laser ablation and downstream microwave plasma has found that 1 mil stressed wires can be safely exposed and examined, showing slip plane fractures in the corner wires. Topside copper metallization remains intact, even the thin protective nickel plating. Sensitive copper metal structures on top of the passivation (such as antennas) will remain electrically viable following decapsulation with plasma, but are often lost and defective following acid decapsulation.

This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the back side of the device as a means of locating metallization defects on flip chip 45nm SOI technology.

In this paper, the application of scanning near-field photon emission microscopy for imaging photon emission sites is demonstrated. Photon emissions generated by a Fin-FET test structure with one metallization layer are imaged with spatial resolution of 50 nm using scattering dialectic probe. The potential applications and limitations of the technique are discussed.

While considerable amount of researches and investigations have been made on lead-free solder joint reliability, limited number of literatures are available on the effect of gold content on lead-free solder joint performance. The challenges of lead-free solder/gold metallization interdiffusion during high temperature application/test are: gold embrittlement, intermetallics growth, void formation, and tin-whisker formation. Tin whiskers causing system failures in earth and space-based applications have been reported. This paper illustrates a few case histories of such challenges. The results confirmed that the synergistic effects of void formation, intermetallic compounds formation due to the thick gold plating, and coefficient of thermal expansion mismatch between organic and ceramic substrates resulted in brittle fracture of the solder joint. The tin whisker formation was attributed to the compressive stress in the tin solder material, which was caused by diffusion of the end-cap metallization, formation of intermetallics, and thermal cycling of the soldered components.

This paper presents a new fail mechanism for laser-marking induced die damage. Discovered during package qualification, silica spheres – commonly used as fillers in the molding material, was shown to act as a propagation medium that promote the direct interaction of the scribing laser beam and the die surface. Critical to the understanding of the fail mechanism is the deprocessing technique devised to allow layer by layer examination of the metallization and passivation layers in an encapsulated silicon die. The technique also made possible the inspection of the molding compound profile directly on top of the affected die area.

In many cases it is difficult to distinguish mechanical damage from electrostatic surface impacts. In recent years, several investigations have resulted in publications on ESDFOS (Electrostatic Discharge From Outside to Surface). While the diagnostics of the phenomena have been worked out quite well for wafers with aluminum metallization, no formal studies on ESDFOS impact to copper-metallized wafers have been published. This paper investigates physical features of Cu-metallized wafers artificially exposed to ESDFOS impacts of variable severity, producing an understanding of damage features to more easily facilitate recognition of EDSFOS events.

The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.

New process will introduce new failure mechanisms during microelectronic device manufacturing. Even if the same defect, its root causes can be different for different processes. For aluminum(Al)-tungsten(W) metallization, the root cause of metal bridging is quite simple and mostly it is blocked etch or under-etch. But, for copper damascene process, the root causes of metal bridging are complicated. This paper has discussed the various root causes of metal bridging for copper damascene process, such as those related to litho-etch issue, copper CMP issue, copper corrosion issue and so on.

In this study, the interface reactions between eutectic SnPb solder and two Ni-based UBM systems are reported, namely the sputtered Cu/Ni(V)/Al and the electroless Au/Ni(P) systems. Comparisons are made to the conventional Au/Al ball bonding system in terms of microstructure evolution, and metallurgical stability. TEM sample preparation is critical in this analysis. The capability of TEM in UBM microstructure studies is demonstrated.

With technology scaling down to sub 0.16um and metalization exceeding 7 levels, the development of reproducible backside silicon sample preparation techniques becomes increasingly important to accurately localize defects. Bulk silicon thinning is a critical step in the backside sample preparation process. This paper will discuss two different ways for silicon thinning: reactive ion etching (RIE) alone, and RIE in conjunction with mechanical milling. In addition, the characterization and optimization of the RIE process for backside silicon thinning will be discussed in this paper. We have found mechanical milling works well for many package types; however, we have had difficulty reproducibly thinning certain package types such as very small die or packages where the wire bonds are in the plane of the silicon die and are in very close proximity to the edge of the die. In these cases, we have found that reactive ion etching (RIE) can be used successfully. We have also found that for package types where mechanical milling works, the combination of mechanical milling and reactive ion etching process is a useful technique for accurately controlling the final thickness of the silicon. This technique combines the speed of mechanically milling and the advantage of RIE process to accurately control the etch rate and etch process in the final stages of thinning the silicon die.