This paper discusses the steps involved in the failure analysis of power semiconductor devices in which leakage currents are observed and can be traced to doping-profile variations in ion-implanted layers. The discovery and assessment of such defects takes knowledge and skill in sample preparation, fault isolation, and the use of advanced inspection techniques, particularly scanning capacitance microscopy, as explained in the paper. Several diodes, MOSFETs, and IGBTs were examined using the proposed approach and the results are presented along with SCM images showing incomplete and poorly shaped ion-implanted structures determined to be the root cause of failure in each case.

This paper explains how tunneling atomic force microscopy (AFM) was used to determine the cause of leakage in FinFETs along the boundary of SRAM cells. The leaking devices were electrically isolated using photoemission microscopy, but conventional FA techniques, including SEM and TEM imaging, found no structural abnormalities. Suspecting that the failures may be due to dopant-related issues, the authors obtained cross sections of both good and bad devices and scanned them in a tunneling AFM. The paper describes the sample preparation process and includes cross-sectional images showing the difference between good and bad transistors. In SRAM areas where no leakage occurred, the fins are well defined and evenly spaced. However, in the area where an emission spot was observed, two of the fins appear to be overlapping, the result of n-well implants that merged.

As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically, especially for implantation related problems [1] [2]. Implantation related defects, or invisible defects, are the most challenging defect types for the application of fault isolation in all of the failure analysis jobs. The key challenge for these kinds of analyses is to make the defect visible. Sometimes, it is difficult or even impossible to visualize the defective point. Then, sufficient electrical evidence and theory analysis are important to bring the issue to resolution. For these kinds of analyses, a nanoprobing system is a necessary tool to conduct the detailed analysis. Combined with the device physics and electrical theory analysis, nanoprobing can bring out the perfect failure mechanism and problematic process step. There are two popular nanoprobing systems in our lab, one is SEM based and the other is AFM based. Both systems have their advantages and disadvantages in the electrical characterization and fault isolation field. In this paper, an implantation related issue was analyzed. Gross leakage was observed on the failed units as compared with good units. Global fault isolation, TIVA and EMMI failed to find the exclusive hotspot. With the GDS and process analysis, the nanoprobing was employed to the performance check on some of the suspected structures. Finally, the defective location was successfully isolated by nanoprobing. Combined with device physics and electrical analysis, the problematic process was successfully isolated.

Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

The accuracy of ion implantation is very important in semiconductor manufacturing and will directly affect the performance of the individual devices and even the whole chip. The deviations of ion implantation energy, dose and angle often result from abnormality of implant equipment or process design limit. The information of ion implantation energy, dose and angle can be qualitatively and quantitatively analyzed by SIMS (Secondary Ion Mass Spectrometry) [1], which provides a way to diagnose ion implanter issue. Based on SIMS analysis results, we can judge whether ion implanter meets the requirements and whether the process design achieves the expected goal. In this paper, we report a SIMS data analysis method determine the deviation of ion implantation angle. A term of deviation rate is defined and a related calculation method was introduced, which is proportional to the deviation angles of the ion implanter. Then, a statistical analysis on a large number of data of deviation rates and ion implantation angles showed that the sampling data followed normal distribution, and thus the corresponding 3 sigma could be obtained. Using the determined 3 sigma range of the deviation rates, we can define the acceptable range for deviation rate. Further, we can use the actual deviation rate to judge if the implant equipment needs maintenance or not, or suggest the direction for improvement. Finally, we set up an oriented and quantitative optimization method of angle deviation by the full mapping of SIMS depth profiles, which can directly set the relationship between the angle deviation and the adjustment parameters of ion implantation disk (Δ alpha, Δ beta). The equipment’s maintenance time and cost can thus be minimized. This method can be used as early detection to the abnormity of ion implant equipment.

This paper explains how the authors used nanoprobing techniques and electrical characterization to trace a die failure to a problem with the photoresist used to mask the wafer for ion implantation. Nanoprobing and leakage current measurements revealed significant differences between the inner and outer fingers of a multi-finger native transistor. Based on simulations, the differences can be attributed to severe scattering at the active edge of the Pwell due to problems with the photoresist, resulting in nonuniform doping profiles and die failure.

The introduction of p+ implanted areas at the drain side of source-drain-gate salicide-blocked electro-static discharge (ESD) protection diodes resulted in a better ESD robustness, however at the expense of increased leakage currents in up to 40% of the 90nm technology test structures. Leaky devices are found to be randomly distributed across a wafer. The leakage current exhibits only weak temperature dependence and is linearly increasing with the p-implanted area. Photoemission microscopy revealed spots located exclusively in the p+ implanted areas. TEM imaging visualized, that the leakage path is caused by dislocations, reaching from the silicon surface through the p+n junction zone into the substrate. Based on these results and the implant conditions, a theory of dislocation formation was postulated and countermeasures had been defined.

For years there has been a discrepancy between the importance of complex doping implantation schemes for advanced technology device performance and the ability to accurately measure the carrier concentrations with the gap widening at each technology node. With scanning spreading resistance Microscopy (SSRM) a major step forward in terms of resolution and quantification was achieved especially since the emergence of full diamond tip manufacturability and improvements in sample preparation techniques. This article discusses the non-trivial prerequisites for this success and some examples from the failure analysis routine that show the promising capabilities of SSRM. The examples include technology monitoring and failure analysis in SOI transistors and vertical surrounded gate transistors, as well as failure analysis on yield and performance issues. SSRM has reached a development stage that allows its application as routine tool for 2D-carrier profiling.

As MOSFET device gate lengths shrink below the 130 nanometer node, the effects of short channel effects (SCE) and gate line edge roughness (LER) have an increasingly more pronounced affect on device performance [1-8, 10]. The 2001 International Technology Roadmap for Semiconductors (ITRS) predicts increasingly tighter critical dimensions (CD) control limits on LER from 2.7 nm in 2004 to 1.3 nm in 2010 [9,11]. As gate lengths shrink, resist etch processes emerge as the most significant contributor to LER [1-8, 11]. In addition, another contributing factor to SCE is junction implant defects. Examples of gate LER effects and junction defects in 130 nanometer node SOI SRAM MOSFET devices identified by sub-micron electrical characterization with analysis by high resolution transmission electron microscopy (TEM) are discussed.

Advances in semiconductor technology are driving the need for new metrology and failure analysis techniques. Failures due to missing, or misregistered implants are particularly difficult to resolve. Two-dimensional implant profiling techniques such as scanning capacitance microscopy (SCM) rely on polish preparation, which makes reliably targeting sub 0.25 um structures nearly impossible.[1] Focused ion beam (FIB) machining is routinely used to prepare site-specific cross-sections for electron microscopy inspection; however, FIB induced artifacts such as surface amorphization and Ga ion implantation render the surface incompatible with SCM (and selective etching techniques). This work describes a novel combination of FIB machining and polish preparation that allows for site-specific implant profiling using SCM.