Using a laser to purposely damage (or zap) a static random-access memory (SRAM) bitcell for bitmap validation purposes is a well-established technique. However, the absence of visible damage in FinFET SRAM cells, amongst other things, makes precision zapping in these devices more difficult. In this paper, we describe system enhancements and a modified workflow for bitmap validation of these devices using precision, near-infrared (NIR) laser-induced damage. We also explore the use of laser perturbation and non-precision zapping options. Examples are provided.

Transmission electron microscopy (TEM) plays an important role in the structural analysis and characterization of materials for process evaluation and failure analysis in the integrated circuit (IC) industry as device shrinkage continues. It is well known that a high quality TEM sample is one of the keys which enables to facilitate successful TEM analysis. This paper demonstrates a few examples to show the tricks on positioning, protection deposition, sample dicing, and focused ion beam milling of the TEM sample preparation for advanced DRAMs. The micro-structures of the devices and samples architectures were observed by using cross sectional transmission electron microscopy, scanning electron microscopy, and optical microscopy. Following these tricks can help readers to prepare TEM samples with higher quality and efficiency.

Several methods are used to invert samples 180 deg in a dual beam focused ion beam (FIB) system for backside milling by a specific in-situ lift out system or stages. However, most of those methods occupied too much time on FIB systems or requires a specific in-situ lift out system. This paper provides a novel transmission electron microscopy (TEM) sample preparation method to eliminate the curtain effect completely by a combination of backside milling and sample dicing with low cost and less FIB time. The procedures of the TEM pre-thinned sample preparation method using a combination of sample dicing and backside milling are described step by step. From the analysis results, the method has applied successfully to eliminate the curtain effect of dual beam FIB TEM samples for both random and site specific addresses.

The corrosion phenomenon was found at the edge area of bond pad under OM images after dicing saw. Experiment showed that the corrosion was related with the feed speed of dicing saw. From SEM and OM results, there were some abnormal contaminations around the corrosive area. Auger and TEM with EDX system were used to characterize the corrosive region and the related Al pad corrosion mechanism was discussed. In this paper, Cu rich and O rich layers were identified by TEM and EDX, which could be induced by galvanic cell reaction.

After wafer-die sawing process, sometimes silicon (Si) dust on microchip Al bondpads is difficult to be cleaned away by DI water, especially at pinhole/corrosive areas caused by galvanic corrosion, thus resulting in non-stick on pads (NSOP) problem in assembly process. To eliminate NSOP problem due to Si dust contamination, in this paper, we will study the mechanism of Si dust contamination and propose a concept of Si dust corrosion. A theoretical model will be introduced so as to explain Si dust contamination and corrosion problem during wafer die sawing process. Based on the mechanism proposed, Si dust contamination and corrosion is related to galvanic corrosion as OH- ions generated from galvanic corrosion will not only react with Al to cause Al corrosion, but also react with Si dust to cause Si dust corrosion. During Si dust corrosion, poly-H2SiO3 and Si-Al-O complex compounds will be formed on Al bondpads, especially at the pinholes/corrosive areas. Poly-H2SiO3 and Si-Al-O complex compounds are “gel-like” material and stick onto the surface of bondpads. It is insoluble in water and difficult to be cleaned away by DI water during or after wafer die sawing process and will cause bondpad discoloration or/and NSOP problem. Some eliminating methods of Si dust contamination and corrosion on Al bondpads during wafer die sawing process are also discussed.

Bond pad metal corrosion was observed during assembly process characterization of a 0.13um Cu microprocessor device. The bond pad consisted of 12kÅ of Al-0.5%Cu atop 9kÅ of Cu, separated by a thin Ta diffusion barrier. The corrosion was first noted after the wafer dicing process. Analysis of the pad surface revealed pitting-type corrosion, consistent with published reports of classic galvanic cell reactions between Al2Cu (theta phase) particles and the surrounding Al pad metal. Analysis of the bond pads on samelot wafers which had not been diced showed higher-thanexpected incidence of hillock and pit hole defects on the Al surface. Statistically designed experiments were formulated to investigate the possibility that the observed pre-saw pad metal defects act as nucleation sites for galvanic corrosion during the sawing process. Analyses of the experimental samples were conducted using optical and scanning electron microscopy, along with focused ion beam deprocessing and energy dispersive X-ray. This paper explores the relationship between the presence of these pre-existing defects and the propensity for the bond pads to corrode during the dicing process, and reviews the conditions under which pit hole defects are formed during the final stages of the Cu-metallized wafer fabrication process. Indications are that strict control of wafer fab backend processes can reduce or eliminate the incidence of such defects, resulting in elimination of bond pad corrosion in the wafer dicing process.

Die cracking is one of the primary failure areas in semiconductor manufacturing and in product longevity. Often die cracking emanates from stress concentrations formed on chips during the dicing process. In order to properly characterize and analyze die cracking relating to the dicing process, we must first properly and accurately quantify and characterize the dicing process. This paper describes the methodology to perform this first step in a premier fashion. In the past, quantification of the dicing process has been a manual operation usually under a microscope. Now there is a new state-of-the-art metrology tool (KIS2010 Inspection System) for quantifying all parameters associated with the dicing process. The system provides computer controlled robotic inspection combined with onboard statistical data reduction software to display results. The goal of this paper is to provide other engineers working in defect and failure analysis an insight into the power of this metrology tool and how it can provide a firm basis for characterizing failures related to the dicing process.