Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. When the remaining silicon is reduced, some redistribution of stress is expected, possibly altering the performance (timing) of integrated circuits in addition to electron-hole pair generation. In this work, a study of the electrical invasiveness due to grinding and polishing silicon integrated circuits to ultra-thin (< 5 um global, ~ 1 um local) remaining thickness is presented.

This paper presents a comparative study of backside sample preparation techniques with applicability to conventional as well as flip chip package types. We will cover mechanical (grinding and milling tools), chemical (wet and dry chemistries) and other approaches such as laser ablation. Backside sample preparation is very challenging. The preparation process flow starts with decapsulation of the ceramic or plastic package, continues with the die paddle removal, silicon thinning and finishes with silicon polishing. The techniques involved include mechanical, chemical and other novel approaches for ceramic and plastic package. Today, only CNC milling can cover the whole process for almost any kind of packages. Nevertheless, photo ablation is a rising technology for package decapsulation. In addition, chemical wet etch can be used to perform silicon thinning and polishing. We will illustrate the complexity of the process through examples. The first one is a ceramic package where the main issue is the hardness of ceramic. The second one is a TSOP package where the main challenge is the chip scaled package. Both will be observed through the IR emission microscope to demonstrate the efficiency of the preparation.

Conventional focused ion beam (FIB) based specific area transmission electron microscopy (TEM) sample preparation techniques usually requires complex grinding and gluing steps before final FIB thinning of the sample to electron transparency (<0.25 μm). A novel technique known as lift-out, plucking or pullout method that eliminates all the pre-FIB sample preparation has been developed for specific area TEM sample preparation by several authors. The advantages of the lift-out procedure include reduced sample preparation time and possibility of specific area TEM sample preparation of most components of integrated circuit with almost no geometric or dimensional limitations. In this paper, details of liftout method, developed during the present work, for site specific x-sectional and a new site specific planar sample preparation are described. Various methodologies are discussed to maximize the success rate by optimizing the factors that affect the technique. In failure analysis, the geometric and dimensional flexibility offered by the lift-out technique can be used to prepare specific area TEM sample of back thinned die, small particles and packaged parts. Such novel applications of lift-out technique in failure analysis are discussed with the examples of TEM results obtained from GaAs and Si based devices. Importantly, it was possible to obtain high resolution lattice images from the lift-out samples transferred on holey carbon supported 3mm copper grids.

Several hundred units were subjected to autoclave stress as part of the qualification of a new fast static RAM. Many units failed after autoclave stress, and these parts recovered after conventional depotting using nitric acid and a hot plate. Based on the recovery of the units, the failures were determined to be fuse-related because the nitric acid cleared the fuse cavities during depotting. Chemical analysis after thermally extracting the die from the package revealed an antimony-rich material in failing fuse cavities. Source of the antimony was linked to antimony trioxide added to the plastic package as a fire retardant. However, it was unclear whether the antimony-rich material caused the failure or if it was an artifact of thermal depotting. A new approach that did not thermally or chemically alter the fuse cavities was employed to identify the failing fuses. This approach used a combination of back-side grinding, dimpling, and back-side microprobing. The antimony-rich material found in the fuse cavity was confirmed using SEM and TEM-based EDS analysis, and it is believed to be a major contributing factor to fuse failures. However, it is unclear whether the short was caused by the antimony-rich material or by a reaction between that material and residual aluminum (oxide) left in the fuse cavity after the laser blows.

A selected area planar TEM (SAPTEM) sample preparation technique for failure analysis of integrated circuits using a transmission electron microscope has been developed. The technique employs a combination of mechanical grinding, selective wet/dry chemical etching (if required) and a two step focused ion beam IIFIB) milling. The mechanical grinding steps include: (a) a backside grind to achieve a die thickness less than 30 µm, (b) the support half ring glue, and (c) a cross-section grind from one side to reach less than 35 pm to the failing site. A selective wet or dry chemical etch is applied before, between,, or after FIB thinning depending on the nature of problem and device components. The FIB milling steps involve: (is) a high ion current cross-sectional cut to reach as close as 5-8 µm to the area of interest (b) a final planar thinning with the ion beam parallel to the surface of the die. The plan view procedure offers unique geometric advantage over the cross-section method for failure analysis of problems that are limited to silicon or certain layers of the device. Iln the cross-sectional approach, a thin section (thickness less than 250 µm) of a device is available for failure analysis, whereas in the planar procedure a 20 µm2 area of any layer (thickness less than 250 µm) of the device is available. The above advantage has been successfully exploited to identify and solve the following prablems in fast static random access memories (FSRAM): (i) random gateoxide rupture that resulted in single bit failures, (ii) random dislocations from the buried contact trenching that caused single bit failures and general silicon defectivity (e.g. implant damage and spacer edge defects), and (iii) interracial reactions.

Laser microchemical (LMC) technology has become an important element of the FIA and debug tool set by supplying key steps not well addressed by previous tools. In this paper we report the optimization of the LMC technology to solve key issues for flip chip FIA. Specific processes have been developed for localized thinning of flip chips, in order to enable access of conventional FIA tools. Additional applications include dramatic enhancement of focused ion beam (FIB) rework and 3-D micromachining for prototyping, in-situ trimming, and mastering of microelectromechanical systems (MEMS). Laser etching of silicon is with a high pressure chlorine assist and is l000X the rate of the fastest focused ion beam methods. In contrast to grinding methods, the process introduces no process stress or contamination and retains an average surface roughness of several hundred angstroms. Micronthickness metal lines are laid down in a one-step vapor phase deposition at 200 μm/s writing speed. Rapid deposition combined with the superior quality of the laser interconnect, translates into writing with a conductance per unit writing time of 1000 to 10,000 times the rate of a focused ion beam.