Failure localization is one of the vital processes in the field of failure analysis. However, as newer fabrication processes emerge and demand for smaller transistors keeps on increasing, the complexity of failure analysis fault isolation involving micro-probing also increases along with the challenges on fault isolation equipment such as limited magnification and susceptibility to vibrations. In this paper, the capability of Focused Ion Beam (FIB) to perform circuit edit was utilized along with Avalon CAD navigation to pinpoint the location of the defects without the need of micro-probing while doing fault isolation. Results showed that through this technique, physical defect locations were successfully identified in three different case studies.

Computer Aided Design (CAD) alignment is a key requirement for dynamic fault isolation. CAD alignment between the drawn layout and the physical reflected image from the device helps to navigate and observe the physical location of the suspected circuitry. Conventionally, large structures such as the boundaries of Static Random-Access Memory (SRAM) cells are used as reference for coarse CAD alignment and the shallow trench isolation (STI) layer is used for fine alignment while analyzing logic cell structures. With technology scaling, especially into FinFETs, the fine alignment has become more challenging as the reflected optical image of STI layer is poorly resolved. In this paper, we discuss the enhanced CAD alignment techniques in Synopsys Avalon that uses features “Minimum object size (dimension based)”, and “net search” developed in the CAD tool, Synopsys Avalon, combined with Amplitude lock-in Dynamic Photon Emission Microscopy (D-PEM) technique to assist a finer CAD alignment.

Automated TEM lamella preparation using the remote CAD to SEM image alignment has been demonstrated for high volume failure analysis. The proposed method not only provides a secure means of using CAD design data during the lamella prep process, but offers an improved flexibility compared to conventional methods of processing CAD design file in a tool environment. The experiment showed that the new method is 3.1 times higher in throughput and requires 74 times less manhours, compared to manual process.

The emergence of heterogenous integration driven by system-in-package (SiP) technology not only increases the complexity of semiconductor failure analysis, but also makes it more difficult to protect intellectual property because of the growing need to share design information to facilitate fault isolation in assembly and test. One way to address these challenges is through a computer-aided design (CAD) database that can be navigated across multiple components without exposing sensitive information. This paper describes the development and use of such a resource and how it enables safe and secure data sharing among supply chain partners.

Semiconductor manufacturing, including the multistep fabrication of ICs and tedious assembly of PCBs, has been outsourced to untrusted regions due to globalization. This invites many problems particularly for PCBs, which are vulnerable to nondestructive methods of attack such as X-ray data collection and surface trace probing. In the case of ICs, high-z materials have proven to be an effective countermeasure to block or scatter X-rays, but PCBs, because of their larger dimensions, are more difficult to fully secure. In this paper, a framework for passively obfuscating the critical connections between components on PCBs is demonstrated. A proof of concept is presented whereby an EDA tool combining the small features of micro electromechanical systems with X-ray simulation and 3D manufacturing processes is used to iteratively optimize a PCB design to thwart reverse engineering and probing attacks.

Defects associated with metal-insulator-metal (MIM) capacitor failures can be difficult to locate using conventional fault isolation techniques because the capacitors are usually buried within a stack of back-end metal layers. In this paper, the authors explain, step by step, how they determined the cause of MIM capacitor failures, in one case, in an overvoltage protection device, and in another, a high-speed digital isolator circuit. The process begins with a preliminary fault isolation study based on OBIRCH or PEM imaging followed by more detailed analyses involving focused ion beam (FIB) cross-sectioning and delayering, micro- or nano-probing, resistive or voltage contrast imaging, and other such techniques.

This study responds to our need to optimize failure analysis methodologies based on laser/silicon interactions, using the functional response of an integrated circuit to local laser stimulation. Thus it is mandatory to understand the behavior of elementary devices under laser stimulation, in order to model and anticipate the behavior of more complex circuits. This paper characterizes and analyses effects induced by a static photoelectric laser on a 90 nm technology PMOS transistor. Comparisons between currents induced in short or long channel transistors for both ON and OFF states are made. Experimental measurements are correlated to Finite Elements Modeling Technology Computer Aided Design (TCAD) analyses. These physical simulations give a physical insight of carriers generation and charge transport phenomena in the devices.

New layout overlay technique has been developed based on standard image correlation techniques to support failure analysis in modern microelectronic devices, which are critical to analyze because they are realized in new technologies using sub-ìm design rules, chemical mechanical polishing techniques (CMP) and autorouted design techniques. As the new technique is realized as an extension of a standard CAD-navigation software and as it makes use of standard image format "TIFF" for data input, which is available at all modern equipments for failure analysis, these technique can be applied to all modern failure analysis methods. Here examples are given for three areas of application: circuit modification using Focused Ion Beam (FIB), support of preparation for backside inspection and fault localization using emission microscopy.

A CAD-based fault diagnosis technique for CMOS-LSI with single fault using abnormal IDDQ has been developed to indicate the presence of physical damage in a circuit. This method of progressively reducingthe faulty portion, works by extracting the inner logic state of each block from logic simulation, and by deriving test vector numbers with abnormal IDDQ. To easily perform fault diagnosis, the hierarchical circuit structure is divided into primitive blocks including simple logic gates. The diagnosis technique employs the comparative operation of each primitive block to determine whether one and the same inner logic state with abnormal IDDQ exists in the inner logic state with normal IDDQ or not. The former block is regarded as normal block and the latter block is regarded as faulty block. The fault of the faulty block can be localized easily by using input logic state simulation. Experimental results on real faulty LSI with 100k gates demonstrated rapid diagnosis times of within ten hours ani reliable extraction of the fault location.