This paper describes how lock-in amplifiers and boxcar averaging can overcome limitations in conventional fault isolation techniques for microelectronic testing. Our approach achieves superior results compared to traditional spectrum analyzer methods through three key applications. First, we measure the signal-to-noise ratio of individual pulses during laser voltage tracing (LVT) across varying pulse widths. Second, we leverage enhanced LVT imaging to improve computer-aided design to stage alignment and laser voltage probe placement—a crucial advancement for analyzing compressed scan and streaming scan network test failures. Finally, we present a case where our Lock-In amplifier system successfully generates pass/fail signals for dynamic laser stimulation in scenarios where conventional test hardware proved inadequate.

Failure localization is one of the vital processes in the field of failure analysis. However, as newer fabrication processes emerge and demand for smaller transistors keeps on increasing, the complexity of failure analysis fault isolation involving micro-probing also increases along with the challenges on fault isolation equipment such as limited magnification and susceptibility to vibrations. In this paper, the capability of Focused Ion Beam (FIB) to perform circuit edit was utilized along with Avalon CAD navigation to pinpoint the location of the defects without the need of micro-probing while doing fault isolation. Results showed that through this technique, physical defect locations were successfully identified in three different case studies.

This paper presents a root cause analysis case study of defective Hall-effect sensor devices. The study identified a complex failure mode caused by chip-package interaction, which has a similar signature to discharging defects such as ESDFOS. However, the study revealed that the defect was induced by local mechanical force applied to IC structures due to the presence of large irregular-shaped filler particles within the mold compound. Extensive failure analysis work was conducted to identify the failure mode, including the development of a new backside analysis strategy to preserve the mold compound during IC defect localization and screening. A combination of different failure analysis techniques was used, including CMP delayering, PFIB trenching, SEM PVC imaging, and large area FIB cross-sectioning. The study found that the mold compound of the package caused thermos-mechanical strain onto the silica filler particle due to epoxy shrinkage during the molding process. Additionally, extra-large, irregularly shaped filler particles (called twin particles), located on top of the chip surface, can cause locally high compression stresses onto the IC layers, initiating cracks in the isolation layers under certain conditions forming a leakage path over the time. Thermo-mechanical finite element analysis was applied to verify the mechanical load condition for these large irregular-shaped filler particles. As a result, an additional polyimide layer was introduced onto the IC to mitigate the mechanical stress of mold compound particles to avoid this failure mode.

Several failures in Chip-On-Lead (COL) package from the customer were returned for Failure Analysis (FA). Containment activities were able to find similar failures. The connectivity of the silicon die to the leads uses gold wire. The die is in live bug position with respect to the package and is being held in place using non-conductive die attach epoxy. The identification of the Failure Mechanism (FMECH) utilized analysis flow involving non-destructive and destructive FA techniques. A hairline crack was found on the die between the two (2) corner pins. Based on lot history reviews, hairline die crack had a very low detectability at electrical test. Further collaboration with the process owners showed the need to identify the crack initiation, propagation and the factors that could result to this FMECH. Analysis of fracture or fractography was utilized in identifying the crack initiation point and propagation. Due to low detectability, identifying the factors resulting to die crack would require several evaluations and process mappings. Finite element analysis (FEA) was utilized to create models and simulation to identify factors that would result to highly stressed area identified through fractography. These additional data for the hairline crack were vital on the identification of root cause and formulation of corrective/preventive actions.

This presentation is an introduction to machine learning techniques and their application in semiconductor failure analysis. The presentation compares and contrasts supervised, unsupervised, and reinforcement learning methods, particularly for neural networks, and lays out the steps of a typical machine learning workflow, including the assessment of data quality. It also presents case studies in which machine learning is used to detect and classify circuit board defects and analyze scanning acoustic microscopy (SAM) data for blind source separation.

Computer Aided Design (CAD) alignment is a key requirement for dynamic fault isolation. CAD alignment between the drawn layout and the physical reflected image from the device helps to navigate and observe the physical location of the suspected circuitry. Conventionally, large structures such as the boundaries of Static Random-Access Memory (SRAM) cells are used as reference for coarse CAD alignment and the shallow trench isolation (STI) layer is used for fine alignment while analyzing logic cell structures. With technology scaling, especially into FinFETs, the fine alignment has become more challenging as the reflected optical image of STI layer is poorly resolved. In this paper, we discuss the enhanced CAD alignment techniques in Synopsys Avalon that uses features “Minimum object size (dimension based)”, and “net search” developed in the CAD tool, Synopsys Avalon, combined with Amplitude lock-in Dynamic Photon Emission Microscopy (D-PEM) technique to assist a finer CAD alignment.

Automated TEM lamella preparation using the remote CAD to SEM image alignment has been demonstrated for high volume failure analysis. The proposed method not only provides a secure means of using CAD design data during the lamella prep process, but offers an improved flexibility compared to conventional methods of processing CAD design file in a tool environment. The experiment showed that the new method is 3.1 times higher in throughput and requires 74 times less manhours, compared to manual process.

In their daily work, engineers in semiconductor Failure Analysis (FA) laboratories generate numerous documents, recording the tasks, findings, and conclusions related to every device they handle. This data stores valuable knowledge for the laboratory that other experts can consult, but being in the form of a collection of documents pertaining to particular devices and their processing history makes it difficult if not practically impossible to find answers to specific questions. This paper therefore proposes a Natural Language Processing (NLP) solution to make the gathering of FA knowledge from numerous documents more efficient. It explains how the authors generated a dataset of FA reports along with corresponding electrical signatures and physical failures in order to train different machine-learning algorithms and compare their performance. Three of the most common classification algorithms were used in the study: K-Nearest Neighbors (kNN), Support Vector Machines (SVM), and Deep Neural Networks (DNN). All of the classification models produced were able to capture patterns associated with different types of failures and predict the causes. The outcomes were best with the SVM classifier and all classifiers did slightly better in regard to physical faults. The reasons are discussed in the paper, which also provides suggestions for future work.

This paper evaluates several approaches for automating the identification and classification of logos on printed circuit boards (PCBs) and ICs. It assesses machine learning and computer vision techniques as well as neural network algorithms. It explains how the authors created a representative dataset for machine learning by collecting variants of logos from PCBs and by applying data augmentation techniques. Besides addressing the challenges of image classification, the paper presents the results of experiments using Random Forest classifiers, Bag of Visual Words (BoVW) based on SIFT and ORB Fully Connected Neural Networks (FCN), and Convolutional Neural Network (CNN) architectures. It also discusses edge cases where the algorithms are prone to fail and where potential opportunities exist for future work in PCB logo identification, component authentication, and counterfeit detection. The code for the algorithms along with the dataset incorporating 18 classes of logos and more than 14,000 images is available at this link: https://www.trusthub.org/#/data .

The emergence of heterogenous integration driven by system-in-package (SiP) technology not only increases the complexity of semiconductor failure analysis, but also makes it more difficult to protect intellectual property because of the growing need to share design information to facilitate fault isolation in assembly and test. One way to address these challenges is through a computer-aided design (CAD) database that can be navigated across multiple components without exposing sensitive information. This paper describes the development and use of such a resource and how it enables safe and secure data sharing among supply chain partners.

Semiconductor manufacturing, including the multistep fabrication of ICs and tedious assembly of PCBs, has been outsourced to untrusted regions due to globalization. This invites many problems particularly for PCBs, which are vulnerable to nondestructive methods of attack such as X-ray data collection and surface trace probing. In the case of ICs, high-z materials have proven to be an effective countermeasure to block or scatter X-rays, but PCBs, because of their larger dimensions, are more difficult to fully secure. In this paper, a framework for passively obfuscating the critical connections between components on PCBs is demonstrated. A proof of concept is presented whereby an EDA tool combining the small features of micro electromechanical systems with X-ray simulation and 3D manufacturing processes is used to iteratively optimize a PCB design to thwart reverse engineering and probing attacks.

Defects associated with metal-insulator-metal (MIM) capacitor failures can be difficult to locate using conventional fault isolation techniques because the capacitors are usually buried within a stack of back-end metal layers. In this paper, the authors explain, step by step, how they determined the cause of MIM capacitor failures, in one case, in an overvoltage protection device, and in another, a high-speed digital isolator circuit. The process begins with a preliminary fault isolation study based on OBIRCH or PEM imaging followed by more detailed analyses involving focused ion beam (FIB) cross-sectioning and delayering, micro- or nano-probing, resistive or voltage contrast imaging, and other such techniques.

This paper presents a machine learning approach that uses genetic algorithms to optimize test program timing sets based on first silicon. The method accounts for test hardware differences, discrepancies in silicon processes, and IO pin interdependency. The general theory and implementation are covered in detail and the capabilities of the method, in terms of false fail discovery, elimination, and failure debug, are demonstrated using actual product test cases.

Global thinning is a technique that enables backside failure analysis and radiation testing. In some devices, it can also lead to increased thresholds for single-event latchup and upset. In this study, we examine the impacts of global thinning on 28 nm node FPGAs. Test devices are thinned to 50, 10, and 3 μm via CNC milling. Lattice damage, in the form of dislocations, extends about 1 μm below the surface, but is removed by polishing with colloidal SiO2. As shown by finite-element modeling, thinning increases compressive global stress in the Si while solder bumps (in flip-chip packages) increase stress locally. The results are confirmed by stress measurements obtained through Raman spectroscopy, although more complex models are needed to account for nonlinear effects in devices thinned to 3 μm and heated to 125°C. Thermal imaging shows that increased local heating occurs with increased thinning, but the maximum temperature difference across the 3-μm die is less than 2°C. Ring oscillators throughout the FPGA fabric slow about 0.5% after thinning and another 0.5% when heated to 125°C, which is attributed to stress changes in the Si.

This presentation is an introduction to machine learning techniques and their application in semiconductor failure analysis. The presentation compares and contrasts supervised, unsupervised, and reinforcement learning methods, particularly for neural networks, and lays out the steps of a typical machine learning workflow, including the assessment of data quality. It also presents case studies in which machine learning is used to detect and classify circuit board defects and analyze scanning acoustic microscopy (SAM) data for blind source separation.

We present a new method for backside integrated circuit (IC) magnetic field imaging using Quantum Diamond Microscope (QDM) nitrogen vacancy magnetometry. We demonstrate the ability to simultaneously image the functional activity of an IC thinned to 12 µm remaining silicon thickness over a wide fieldof- view (3.7 x 3.7 mm 2 ). This 2D magnetic field mapping enables the localization of functional hot-spots on the die and affords the potential to correlate spatially delocalized transient activity during IC operation that is not possible with scanning magnetic point probes. We use Finite Element Analysis (FEA) modeling to determine the impact and magnitude of measurement artifacts that result from the specific chip package type. These computational results enable optimization of the measurements used to take empirical data yielding magnetic field images that are free of package-specific artifacts. We use machine learning to scalably classify the activity of the chip using the QDM images and demonstrate this method for a large data set containing images that are not possible to visually classify.

Getting accurate fault isolation during failure analysis is mandatory for success of Physical Failure Analysis (PFA) in critical applications. Unfortunately, achieving such accuracy is becoming more and more difficult with today’s diagnosis tools and actual process node such as BCD9 and FinFET 7 nm, compromising the success of subsequent PFA done on defective SoCs. Electrical simulation is used to reproduce emission microscopy, in our previous work and, in this paper, we demonstrate the possibility of using fault simulation tools with the results of electrical test and fault isolation techniques to provide diagnosis with accurate candidates for physical analysis. The experimental results of the presented flow, from several cases of application, show the validity of this approach.

The continuously growing demands in high-density memories drive the rapid development of advanced memory technologies. In this work, we investigate the HfOx-based resistive switching memory (ReRAM) stack structure at nanoscale by high resolution TEM (HRTEM) and energy dispersive X-ray spectroscopy (EDX) before and after the forming process. Two identical ReRAM devices under different electrical test conditions are investigated. For the ReRAM device tested under a regular voltage bias, material redistribution and better bottom electrode contact are observed. In contrast, for the ReRAM device tested under an opposite voltage bias, different microstructure change occurs. Finite element simulations are performed to study the temperature distributions of the ReRAM cell with filaments formed at various locations relative to the bottom electrode. The applied electric field as well as the thermal heat are the driving forces for the microstructure and chemical modifications of the bottom electrode in ReRAM deceives.

A typical workflow for advanced package failure analysis usually focuses around two key sequential steps: defect localization and defect characterization. Defect localization can be achieved using a number of complementary techniques, but electro optical terahertz pulse reflectometry (EOTPR) has emerged as a powerful solution. This paper shows how the EOTPR approach can be extended to provide solutions for the growing complexity of advanced packages. First, it demonstrates how localization of defects can be performed in traces without an external connection, through the use of an innovative cross-sectional probing with EOTPR. Then, the paper shows that EOTPR simulation can be used to extract the interface resistance, granting an alternative way of quantitative defect characterization using EOTPR without the destructive physical analysis. These novel approaches showed the great potential of EOTPR in failure analysis and reliability analysis of advanced packaging.

Scanning Microwave Impedance Microscopy (sMIM) can be used to characterize dielectric thin films and to quantitatively discern film thickness differences. FEM modeling of the sMIM response provides understanding of how to connect the measured sMIM signals to the underlying properties of the dielectric film and its substrate. Modeling shows that sMIM can be used to characterize a range of dielectric film thicknesses spanning both low-k and medium-k dielectric constants. A model system consisting of SiO2 thin films of various thickness on silicon substrates is used to illustrate the technique experimentally.