This paper provides an overview of the semiconductor analysis process at BMW. It explains how it was developed and how it differs from the failure analysis process used in semiconductor fabs. It describes the general process flow from first analyses through descending levels of localization at different length scales. It discusses sample preparation procedures, test methods and equipment, and advanced techniques. In the work presented here, the authors explain how they combined ToF-SIMS with STEM lamella preparation in a FIB-SEM, which allowed them to correlate concentration variances in an underlying layer with surface anomalies discovered during light microscope inspection.

3D X-ray tomography plays a critical role in electronic device failure analysis, but it can take several hours to overnight to get sufficient resolution in fault regions to detect and identify defects. In this paper, we propose a machine learning based reconstruction technique that can speed up data acquisition by a factor of four or more, while maintaining image quality. The method, which uses neural networks, extracts signals from low-dose data more efficiently than the conventional Feldkamp-Davis-Kress (FDK) approach, which is sensitive to noise and prone to aliasing errors. Several semiconductor packages and a commercial smartwatch battery module are analyzed using the new technique and the results compared with those obtained using conventional methods. The neural network can be trained on as little as one tomography image and the only requirement for the training data is that the sample or region of interest is well represented with all characteristic features in the field-of-view.

Printed Circuit Boards (PCBs) play a critical role in everyday electronic systems, therefore the quality and assurance of the functionality for these systems is a topic of great interest to the government and industry. PCB manufacturing has been largely outsourced to cut manufacturing costs in comparison with the designing and testing of PCBs which still retains a large presence domestically. This offshoring of manufacturing has created a surge in the supply chain vulnerability for potential adversaries to garner access and attack a device via a malicious modification. Current hardware assurance and verification methods are based on electrical and optical tests. These tests are limited in the detection of malicious hardware modifications, otherwise known as Hardware Trojans. For PCB manufacturing there has been an increase in the use of automated X-ray inspection. These inspections can validate a PCB’s functionality during production. Such inspections mitigate process errors in real time but are unable to perform highresolution characterization on multi-layer fully assembled PCBs. In this paper, several X-ray reconstruction methods, ranging from proprietary to open-source, are compared. The high-fidelity, commercial NRecon software for SkyScan 2211 Multi-scale X-ray micro-Tomography system is compared to various methods from the ASTRA Toolbox. The latter is an open-source, transparent approach to reconstruction via analytical and iterative methods. The toolbox is based on C++ and MEX file functions with MATLAB and Python wrappers for analysis of PCB samples. In addition, the differences in required imaging parameters and the resultant artifacts generated by planar PCBs are compared to the imaging of cylindrical biological samples. Finally, recommendations are made for improving the ASTRA Toolbox reconstruction results and guidance is given on the appropriate scenarios for each algorithm in the context of hardware assurance for PCBs.

The development of a characterization workflow for reliable pore characterization of porous metals especially for microelectronics applications is very important. This will help to provide design guidelines for the production and for the improved reliability of the devices. In this paper, we set up a workflow to accurately evaluate the porosity, of four different porous copper materials. The porous thin films are fabricated by using stencil printing. Within the workflow we use for the measurement non-destructive micro-X-ray computed tomography (ƒÝ-XCT) and destructive high-resolution scanning electron focused ion beam nano-tomography (nano-FIB tomography). The latter will be also used to calibrate the threshold for the ƒÝ-XCT image data, since a direct evaluation of the porosity from the non-destructively obtained ƒÝ-XCT image data due to resolution and contrast is not possible. Therefore, we develop an indirect histogram based evaluation method to get the porosity of the porous copper thin films. We validate and discuss the obtained results with respect to further studies.

An effective method is presented to locate certain failure sites on exposed junction of insulated-gate bipolar transistor (IGBT) devices. High emitter to collector leakage current, hereafter called ICESR, is an IGBT failure mode. The leakage current is typically related to the exposed P+/N+ junction on the die sidewall. Solder die attach residue bridging or silicon damage at this exposed P+/N+ junction are common causes of ICESR leakage. The die attach residue can be dislodged during decapsulation resulting in loss of failure information. A failure analysis flow will be described to precisely locate the ICESR leakage site without disturbing any possible die attach residue.

3D integration takes more and more importance in the microelectronics industry. This paper focuses on two types or objects, which are copper pillars (25 micrometer of diameter) and hybrid bonding samples. It aims at a statistical morphology observation of hybrid bonding structures, which underwent an electromigration test at 350 deg C and 20 mA. The goal of the study is two-fold. It is both to limit the overall time needed to perform a whole process flow, from sample preparation to reconstructed volume, and to limit the time of human intervention. To achieve this goal, three strategies are presented: improving the sample preparation scheme, reducing the number of projections with iterative algorithms and the Structural SIMilarity function, and automating the post-processing. The post-processing of the data is fully automated and directly renders the reconstructed volume. The high signal to noise ratio allows for further segmentation and analysis.

This paper discusses the development of an extensible programmatic workflow that leverages evolving technologies in 2D/3D imaging, distributed instrument control, image processing, and automated mechanical/chemical deprocessing technology. Initial studies involve automated backside mechanical ultra-thinning of 65nm node IC processor chips in combination with SEM imaging and X-ray tomography. Areas as large as 800μm x 800μm were deprocessed using gas-assisted plasma FIB delayering. Ongoing work involves enhancing the workflow with “intelligent automation” by bridging FIB-SEM instrument control and near real-time data analysis to establish a computationally guided microscopy suite.

Reverse engineering of electronic hardware has been performed for decades for two broad purposes: (1) honest and legal means for failure analysis and trust verification; and (2) dishonest and illegal means of cloning, counterfeiting, and development of attacks on hardware to gain competitive edge in a market. Destructive methods have been typically considered most effective to reverse engineer Printed Circuit Boards (PCBs) – a platform used in nearly all electronic systems to mechanically support and electrically connect all hardware components. However, the advent of advanced characterization and imaging tools such as X-ray tomography has shifted the reverse engineering of electronics toward non-destructive methods. These methods considerably lower the associated time and cost to reverse engineer a complex multi-layer PCB. In this paper, we introduce a new anti–reverse engineering method to protect PCBs from non-destructive reverse engineering. We add high-Z materials inside PCBs and develop advanced layout algorithms, which create inevitable imaging artifacts during tomography, thereby making it practically infeasible for an adversary to extract correct design information with X-ray tomography.

To get both the resolution and the field of view needed, 3Di devices are characterized in this paper using phase-contrast X-ray tomography performed in a synchrotron source. The paper shows how the synchrotron-based tomography can be routinely used as a tool for failure analysis, and how some strategies can be applied to make those analyses more time-efficient and automatic without any loss of resolution. It presents and assesses the possibilities offered by a synchrotron radiation facility such as European Synchrotron Radiation Facility for the field of failure analysis in microelectronics. The paper illustrates those possibilities through two main examples, based on two different types of connection of bottom and top tiers in 3D integration, either thermocompression with copper pillars or hybrid bonding using copper pads. Several strategies have been successfully tested for the data acquisition to be faster and to limit the needed human intervention as much as possible.

Prior to x-ray tomography, cylindrically-shaped samples are obtained using an innovative milling strategy on a Plasma-FIB. The method presented consists of tuning the ion dose as a function of pixel coordinates along with optimization of the scan geometries, drastically reducing the preparation time and significantly improving the overall workflow efficiency.

Bond pull testing, a well-known method in the failure analysis community, is used to evaluate the integrity of an electronic microchip as well as to detect counterfeit ICs. Existing bond pull tests require that the microchip be de-capsulated in order to obtain physical access to the bond wires in the IC package. Bond pull analysis based on simulation and finite element methods also exists but relies on the original model for a bond wire from a CAD design. In this work, we introduce X-ray tomography imaging with 700nm imaging resolution to acquire the 3D geometry details of bond wires non-destructively. Such information can be used to develop more accurate models for finite element analysis based on real size and structure. Therefore, one can test the bond wire strength as a proof of concept for virtual mechanical testing and counterfeit detection in microchips.

It is known by both the commercial and government suppliers, one of the best ways to guarantee the security and reliability of IC's is to image the IC directly using an x-ray microscope. These images can be inspected for many signs of counterfeit electronics. Unfortunately, previous generations of x-ray imaging systems have not kept up with the increasingly sophisticated counterfeiting techniques. Traditional 2D X-ray inspection techniques are becoming inadequate for imaging and verifying features due to the limited resolution of these systems for thick samples and because 2D images contain too many overlapping features to easily discern, making identification very difficult. This paper discusses the development of advanced sample preparation techniques for counterfeit IC detection. It presents information on the limitations of X-ray imaging and 3D tomographic reconstruction, and on the models for resolution configuration improvement.

X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

Reverse engineering of electronics systems is performed for various reasons ranging from honest ones such as failure analysis, fault isolation, trustworthiness verification, obsolescence management, etc. to dishonest ones such as cloning, counterfeiting, identification of vulnerabilities, development of attacks, etc. Regardless of the goal, it is imperative that the research community understands the requirements, complexities, and limitations of reverse engineering. Until recently, the reverse engineering was considered as destructive, time consuming, and prohibitively expensive, thereby restricting its application to a few remote cases. However, the advents of advanced characterization and imaging tools and software have counteracted this point of view. In this paper, we show how X-ray micro-tomography imaging can be combined with advanced 3D image processing and analysis to facilitate the automation of reverse engineering, and thereby lowering the associated time and cost. In this paper, we demonstrate our proposed process on two different printed circuit boards (PCBs). The first PCB is a four-layer custom designed board while the latter is a more complex commercial system. Lessons learned from this effort can be used to both develop advanced countermeasures and establish a more efficient workflow for instances where reverse engineering is deemed necessary. Keywords: Printed circuit boards, non-destructive imaging, X-ray tomography, reverse engineering.

The X-ray inspection of fully assembled samples is becoming ever more important as the benefits of using area array packages/chip scale packages/flip chips are applied to more and more products. Sample preparation has traditionally been used to improve access to geometry or a specific location with a known defect that requires verification. The novel paradigm is an integrated approach to sample preparation and X-ray inspection to optimize resolution and throughput time performance with minimally deprocessed sample. This paper, covering the limitations of X-Ray imaging and 3D tomographic reconstruction, discusses the development of models for throughput time and resolution by failure analysis labs. It also discusses the processes involved in advanced sample preparation techniques and global BGA removal to obtain improved resolution at die level.

We have exploited an innovative X-ray tomography system, which is hosted in a Scanning Electron Microscope (SEM). The resolution reached by this equipment is closed to 160nm in 2 dimensions. We imaged Through Silicon Vias (TSV) which have undergone a manufacturing defect and characterized voids within these interconnections.

Failure analysis of electronic components is almost always destructive, and there’s no going back once a destructive step is performed. Or, that’s the way it used to be, before the development of some of the more sophisticated nondestructive techniques such as computed tomography (CT). This paper presents a case study of an optocoupler, the suspected failure of which could not be confirmed until the last day of the month-long analysis, when the cause of failure was conclusively determined by a CT model captured weeks earlier.

We developed the non-destructive failure analysis method that is combination of Lock-in thermography (LIT) and high resolution 3D oblique CT. It made possible to complete the total analysis efficiently, because we can distinguish the type of failure by this non-destructive method.

The 3D package configuration presents challenges to conventional Fault Isolation (FI) and Failure Analysis (FA) methods. This paper illustrates that with correct Electro Optical Terahertz Pulse Reflectometry (EOTPR) data processing, interpretation and additional reference spectra, the combination of EOTPR to isolate the open/high resistance failure location and 3D X-ray Computed Tomography (CT) to image the failure is very effective for System in a Package (SIP) FI/FA.

The continuous miniaturization trends followed by a vast majority of electronic applications results in always denser PCBs (Printed Circuit Board) designs and PCBAs (Printed Circuit Board Assembly) with increasing solder joint densities. Current high-end designs feature high layer count sequential build-up PCBs with fine lines/spaces and numerous stacked filled microvias, as well as closely spaced BGA/QFN components with pitches down to 0.4mm. In recent years, several 3D packaging approaches have emerged to further increase system integration by enabling the stacking of several dies or packages. This has translated for example into the advent of highly integrated complex System in Package (SiP) modules, Package-on-Package (PoP) assemblies or chips embedded in PCBs [1]. From a failure analysis (FA) perspective, this deep technology evolution is setting extreme challenges for accurately locating a failure site, especially when destructive techniques are not desired. The few conventional non-destructive techniques like optical or x-ray inspection are now practically becoming useless for high density PCB designs. This paper reviews several advanced analysis techniques that could be used to overcome these limitations. It will be shown through several examples how three non-destructive methods usually dedicated to package analyses can be efficiently adapted to PCBs and PCBAs: • Scanning Acoustic Microscopy (SAM) • 3D X-ray Computed Tomography (CT) • Infrared Thermography A case study of a flex-rigid board FA is presented to show the efficiency of these three techniques over classical techniques. In this example, not only the defect localization has been possible, but also the defect characterization without using destructive analysis.