An advanced technique for site-specific Atom Probe Tomography (APT) is presented. An APT sample is prepared from a targeted semiconductor device (commercially available product based on 14nm finFET technology). Using orthogonal views of the sample in STEM while FIB milling, a viable APT sample is created with the tip of the sample positioned over the lightly-doped drain (LDD) region of a pre-defined PFET. The resulting APT sample has optimal geometry and minimal amorphization damage.

Focused ion beam (FIB) microscopy is an essential technique for the site-specific sample preparation of atom probe tomography (APT). The site specific APT and automated APT sample preparation by FIB have allowed increased APT sample volume. In the workflow of APT sampling, it is very critical to control depth of the sample where exact region of interest (ROI) for accurate APT analysis. Very precise depth control is required at low kV cleaning process in order to remove the damaged layer by previous high kV FIB process steps. We found low kV cleaning process with 5 kV and followed by 2kV beam conditions delivers better control to reached exact ROI on Z direction. This understanding is key to make APT sample with fully automated fashion.

In this paper, impact of carbon on threshold voltage in MOSFET-based device is studied by 3D-atom probe tomography (APT). Carbon is one of most difficult contaminants incorporated from fab-environment to be detected by typical analytical techniques such as TEM-EDS or SIMS. Here, we successfully demonstrated the detection of carbon segregated at gate oxide/Si substrate interface using 3D-APT with single-atom sensitivity and sub-nanometer spatial resolution. It was found that the carbon contaminants have significant effect on the threshold voltage shift (ΔVth), in which ΔVth increases slightly with increasing carbon concentration. The deterioration of device performance is explained by means of which the positively ionized carbons at the interface acting as additional positive charges affecting the inversion to n-channel.

As semiconductor device geometries shrink due to process technology development and circuit density rapidly increases, it is becoming extremely difficult to effectively analyze defects. Against this background, more precise and efficient techniques to analyze the root cause of defects is in constant demand. This paper proposes a method to quickly and accurately identify the true cause of device failure by using a nano probe EBAC/EBIC analysis technique. The most significant benefit of the EBAC/EBIC analysis technique is the ability to identify normal or abnormal circuit behavior with an intuitive image. This benefit can minimize the damage to a sample during the initial analysis phase, which has been an issue in the analysis of existing physical properties of semiconductors. In this paper, we identified the root cause of a series transistor defect in CIS (CMOS Image Sensor) product by using EBAC/EBIC (analysis) technique, and verified this with the assistance of SSRM (Scanning Spreading Resistance Microscopy) and APT (Atomic Probe Tomography). By doing so, we confirmed that the analysis technique proposed in this paper is very effective in identifying and pinpointing the true cause and location of the defect.

Continuing advances in Atom Probe Tomography and Focused Ion Beam Scanning Electron Microscope technologies along with the development of new specimen preparation approaches have resulted in reliable methods for acquiring 3D subnanometer compositional data from device structures. The routine procedure is demonstrated here by the analysis of the silicon-germanium source-drain region of a field effect transistor from a de-packaged off-the-shelf 28 nm design rule graphics chip. The center of the silicon-germanium sourcedrain region was found to have approximately 180 ppm of boron and the silicide contact was found to contain both titanium and platinum.

There are many opportunities in semiconductor processing where atom probe tomography (APT) analysis of a finished product is desirable; competitive analysis and failure analysis are two good examples, and only recently have APT results been obtained from fully processed "off-the-shelf" transistor structures that are part of a finished product. This paper explores the feasibility of APT analysis for fully packaged integrated-circuit microelectronic devices by detailing the various options available in specimen preparation and the resulting analyses. The goal of this work is to take an off-the-shelf microelectronics product and perform APT analysis on various device-level components. This work demonstrates that a wealth of high quality information may be obtained from site-specific APT analysis of post-production microelectronic devices. The yield of useful results from such analyses has not yet been determined, but the small number of specimens analyses (four) yielded quality results in the first attempt.

Doping profile measurements in extremely small features like transistor gates or source/drain regions is a challenging task for the semiconductor industry. In our article, we successfully used an atom probe tomography (APT) tool to measure the doping concentration and profile of the dopant elements in a commercial 65 nm product. APT not only delivers doping concentrations but also gives the highest spatial resolution (sub-1 nm) three-dimensional compositional information of any microscopy technique.