Currently gaps in non-destructive 2D and 3D imaging in PFA for advanced packages and MEMS exist due to lack of resolution to resolve sub-micron defects and the lack of contrast to image defects within the low Z materials. These low Z defects in advanced packages include sidewall delamination between Si die and underfill, bulk cracks in the underfill, in organic substrates, Redistribution Layer, RDL; Si die cracks; voids within the underfill and in the epoxy. Similarly, failure modes in MEMS are often within low Z materials, such as Si and polymers. Many of these are a result of mechanical shock resulting in cracks in structures, packaging fractures, die adhesion issues or particles movements into critical locations. Most of these categories of defects cannot be detected non-destructively by existing techniques such as C-SAM or microCT (micro x-ray computed tomography) and XRM (X-ray microscope). We describe a novel lab-based X-ray Phase contrast and Dark-field/Scattering Contrast system with the potential to resolve these types of defects. This novel X-ray microscopy has spatial resolution of 0.5 um in absorption contrast and with the added capability of Talbot interferometry to resolve failure issues which are related to defects within organic and low Z components.

FA cannot consist of simply jumping to conclusions. The FA process is validated through correlation with the initial failure and through interpretation of the obtained results, subjective by definition. This paper illustrates the difficulty of analyzing complex failures caused by multiple factors, including wafer fabrication, assembly, and application conditions. Inter-Layer Dielectric (ILD) delamination was experienced on various ICs from the same 250nm technology. A complete set of techniques (C-SAM, laser and optical microscopy, SEM, FIB cross-sections, TEM, EFTEM, SIMS, Auger, delineation) was used as different pieces of the same puzzle to reveal the multiple factors contributing to the ILD delamination failures. Due to the subtle nature of some of the underlying causes, defining an accurate FA approach with appropriate sample preparation and accurate device traceability was critical to understanding this complex, multivariate issue.

Lifted bond balls in Integrated Circuit (IC) have numerous failure mechanisms. A simple external curve can confirm the open, and with package decapsulation, lifted balls can be readily observed. However, the exact cause can be difficult to identify. Most often, a cross section through the balls was performed, but it is far from being able to reveal the reason for lifted bond balls. A comprehensive FA approach is needed. Performing failure analysis through the back side of the die using Scanning Acoustic Microscopy (C-SAM) and Infra Red (IR) inspection helps to observe the conditions of the bond pads. Pulling the die from the mold compound can provide a pristine view of the bond ball-bond pad interface. This allows the detection of contaminants, both organic and inorganic, which cross sections cannot provide.

Fault isolation and failure analysis for Si related issues in microelectronic packages need non-destructive and high resolution techniques to reduce the analysis time. This paper illustrates non-destructive and high resolution CSAM techniques, which are shown to be very effective in subtle thin film defect and die edge defect CSAM imaging.

Counterfeit components have been defined as a growing concern in recent years as demand increases for reducing costs. In fact the Department of Commerce has identified a 141% increase in the last three years alone. A counterfeit is any item that is not as it is represented with the intention to deceive its buyer or user. The misrepresentation is often driven by the known presence of defects or other inadequacies in regards to performance. Whether it is used for a commercial, medical or military application, a counterfeit component could cause catastrophic failure at a critical moment. The market for long life electronics, based on commercial off the shelf (COTS) parts, such as those used in medical, military, commercial depot repair, or long term use applications (e.g. street and traffic lights, photovoltaic systems), seems to create a perfect scenario for counterfeiters. With these products, components wear out and need to be replaced long before the overall product fails. The availability of these devices can be derived in many ways. For example, a typical manufacturer may render a component obsolete by changing the design, changing the functionality, or simply discontinuing manufacture. Also, the parts that are available after a design has been discontinued are often distributed by brokers who have very little control over the source or supply. Recycling of devices has also emerged as a means of creating counterfeit devices that are presented as new. And finally, as demand and price increase, the likelihood of counterfeits also increases. This paper will address the four unique sources of counterfeit components and insight into how they occur. Detection methodologies, such as visual inspection, mechanical robustness, X-Ray, XRF, C-SAM, Infrared Thermography, electrical characterization, decapsulation, and marking evaluations, will be compared and contrasted, as well as multiple examples of counterfeit parts identified by DfR.

The electronics supply chain is being increasingly infiltrated by non-authentic, counterfeit electronic parts, whose use poses a great risk to the integrity and quality of critical hardware. There is a wide range of counterfeit parts such as leads and body molds. The failure analyst has many tools that can be used to investigate counterfeit parts. The key is to follow an investigative path that makes sense for each scenario. External visual inspection is called for whenever the source of supply is questionable. Other methods include use of solvents, 3D measurement, X-ray fluorescence, C-mode scanning acoustic microscopy, thermal cycle testing, burn-in technique, and electrical testing. Awareness, vigilance, and effective investigations are the best defense against the threat of counterfeit parts.

The present paper studies several failure mechanisms at both UBM and Cu substrate side for flip-chip die open contact failures in multi-chip-module plastic BGA-LGA packages. A unique failure analysis process flow, starting from non-disturbance inspection of x-ray, substrate and die level C-SAM, bump x-section followed by a bump interface integrity test including under-fill etching and bump pull test and/or substrate etch has been developed. Four different types of failure mechanism in multiple chip module that are associated with open/intermittent contact, ranging from device layout design, UBM forming process defect, to assembly related bump-substrate interface delamination have been identified. The established FA process has been proved to be efficient and accurate with repeatable result. It has facilitated and accelarated new product qualification processes for a line of high power MCM modules.

This paper reports using Scanning Acoustic Microscopy for solder joint failure analysis and process and design improvements. There are reliability concerns associated with solder voids or non-wetting of the solder to the bond pads which is particularly important for higher electrical power or temperature applications. Defects in solder can also occur and grow during operation and thermal cycling. Sonoscan is an attractive non-destructive test to characterize solder joints and is often used to study the growth of defects during life test simulations. X-ray imaging cannot identify very small defects, particularly non-wetting and delamination because of poor resolution. The instrument used in this study was a CSAM (C-Mode Scanning Acoustic Microscopy) operating in reflection mode at 30-100 MHz. We have identified voids inherent in the solder layer as well as delamination at the package to solder and solder to heat-sink interfaces. C-SAM results confirmed that the delamination was caused by CTE mismatch of the materials as well as the mechanical stresses caused by higher level package integration and module assemblies. Thermal cycling studies have shown that typically the voids do not grow whereas delamination does. These results were used to improve thermal heat-sinking and product reliability by minimizing defects in solder joint by changes in process and mechanical designs.

The present paper is a study on flip-chip open bump failure mechanism. Initial electrical testing showed open circuit condition. Scanning acoustic microscope (C-SAM) identifies delamination on particular bump(s). Initial cross-sectional images suggested that the separation took place at Al – TiW interface. However, EDS analysis on the separated surface indicated the presence of Al metal at both sides of the separation, which raises a question of why the Al layer is cracked or separated instead of interface de-lamination. Research in literature and investigation at assembly line points an ultrasonic cleaning step in manufacturing process as a contributor to the open bump failure. Examining virgin dice after bump removal observed crack in nitride passivation around the bump neck, indicating high stress level during passivation film deposition and/or bump formation process. Hence it is concluded that ultrasonic cleaning in device assembly aggravates preexisting stress in weak bump(s), resulting in latent failure in field application.

For stacked die package delamination inspection using C-mode acoustic microscope, traditional interface and thorough scan techniques cannot give enough of information when the delamination occurs in multi-interfaces, and echoes from adjacent interfaces are not sufficiently separated from each other. A thinner thickness in the stacked-die package could complicate C-mode scanning acoustic microscopy (CSAM) analysis and sometimes may lead to false interpretations. The first objective of this paper is to briefly explain the CSAM mechanism. Based on that, some of the drawbacks of current settings in detecting the delamination for stacked-die packages are presented. The last objective is to introduce quantitative B-scan analysis mode (Q-BAM) and Zip-Slice technologies in order to better understand and improve the reliability of detecting the delamination in stacked-die packages. Therefore, a large portion of this paper focuses on the Q-BAM and Zip-Slice data acquisition and image interpretation.

Solder bumps are frequently the sites of defects that cause continuity failures in ceramic flip chip packages. In concurrent technology the solder bump is a multi-layered structure containing several interfaces. Conventional c-SAM imaging alone cannot delineate subtle bump defects. In this article we present experimental results that document the nature of interface defects in multi-layered solder bumps as well as their acoustic signatures. The acoustic signatures obtained from defective bumps are contrasted with the signals obtained from pristine bumps and the sensitive nature of these signatures to defects is highlighted.

The quality of the die attach is crucial for almost all power devices, as in most cases thermal and electrical transport is vertical through the die and its backside. For glue inspection, C-SAM through the lead frame is widely used. Ordinarily, one of the three following states of delamination is found: (A) no delamination, (B) delamination at the die, or (C) delamination at the lead frame. A general rule for the assignment of the brightness in C-SAM amplitude images to these states of delamination cannot be given. This is evidenced by contrast inversions observed with frequency variation of the applied ultrasound or variation of the glue thickness. Contrast inversions at images through the lead frame occur between areas of states (A) and (B). The calculation of ultrasonic echoes for a three-layer model (copper, glue, silicon) shows that the contrast inversions are connected to the first resonance of the glue in state (B). Here complicated shapes of the echoes are found in experiments and calculations, which helps to correctly assign brightness levels to delamination states. Additionally a flow for reliable glue investigation with the use of through-transmission SAM inspection is proposed.

Surface Mount Technology (SMT) ceramic capacitors are widely used on virtually every type of electronic product. In computer systems, SMT capacitors populate the majority of electronic parts found on each Printed Circuit Assembly (PCA) within the product, primarily as bypass or coupling devices between power and ground. As such, the opportunity for failure is substantially higher than with other commonly used active or passive components. Additionally, the relatively small ceramic bodies are prone to mechanical damage. Their proportionately high numbers, sensitivity to mechanical stress and difficulty in isolating to a specific failing device on the PCA (since many of these parts are in parallel with many other identical capacitors) all combine to make the successful isolation and analysis of the root cause of failure particularly difficult for the failure analyst. Often, the cause of failure is misdiagnosed, or the evidence is compromised by the methods used to perform the analysis. This paper will discuss the common failure mechanisms associated with SMT ceramic capacitors, as well as some innovative non-destructive isolation tools and techniques, including C-Mode Scanning Acoustic Microscopy (C-SAM), Infrared thermography (IR) and Micro-Focus X-ray analysis. Several case studies will be cited which demonstrate each of the mechanisms and methods. Additionally, the processes used to properly analyze these defects will be examined.

This paper describes a new diagnostic technique for analyzing microstructural changes occurring to flip chip joints after accelerated thermal tests. Flip chip reliability was assessed at high temperatures, with and without the application of electrical bias. A combination of standard metallurgical polishing techniques and the use of a focused ion beam (FIB) lift out technique was employed to make site-specific samples for transmission electron microscopy (TEM) cross-sections. We studied evaporated 95Pb/5Sn bumps, on sputtered Cr/CrCu/Cu/Au as the under bump metallization (UBM). Thermally stressed samples were tested for electrical continuity and evaluated using 50 MHz C-mode scanning acoustic microscopy (C-SAM). Failed samples were crosssectioned and large voids at the UBM were observed optically. TEM specimens taken from the predefined UBM region of degraded flip chip devices provided critical microstructural information, which led to a better understanding of a cause of degradation occurring in the flip chip joints.

With the increasing complexity of packaging technology, especially Flip-chip, package failure analysts face challenges to identify failure root cause. Due to the complex construction of Flip-chip packages, the conventional failure analysis process flow needs to be enhanced. Thus, generating a bench marked failure analysis process flow specifically for Flip-chip packaged devices becomes necessary. In this paper, the failure analysis process flow for Flip-chip package devices along with different failure mechanisms will be discussed and demonstrated. For instance, even in a simple continuity-open failure, instead of cross-sectioning the device as the initial fault identification step, the process flow details how to start from non-destructive C-SAM, TDR, to destructive die removal, polishing and finally cross-sectioning.

Integration of circuits on semiconductor devices with resulting increase in pin counts is driving the need for improvements in packaging for functionality and reliability. One solution to this demand is the Flip- Chip concept in Ultra Large Scale Integration (ULSI) applications [1]. The flip-chip technology is based on the direct attach principle of die to substrate interconnection.. The absence of bondwires clearly enables packages to become more slim and compact, and also provides higher pin counts and higher-speeds [2]. However, due to its construction, with inherent hidden structures the Flip-Chip technology presents a challenge for non-destructive Failure Analysis (F/A). The scanning acoustic microscope (SAM) has recently emerged as a valuable evaluation tool for this purpose [3]. C-mode scanning acoustic microscope (C-SAM), has the ability to demonstrate non-destructive package analysis while imaging the internal features of this package. Ultrasonic waves are very sensitive, particularly when they encounter density variations at surfaces, e.g. variations such as voids or delaminations similar to air gaps. These two anomalies are common to flip-chips. The primary issue with this package technology is the non-uniformity of the die attach through solder ball joints and epoxy underfill. The ball joints also present defects as open contacts, voids or cracks. In our acoustic microscopy study packages with known defects are considered. It includes C-SCAN analysis giving top views at a particular package interface and a B-SCAN analysis that provides cross-sectional views at a desired point of interest. The cross-section analysis capability gives confidence to the failure analyst in obtaining information from a failing area without physically sectioning the sample and destroying its electrical integrity. Our results presented here prove that appropriate selection of acoustic scanning modes and frequency parameters leads to good reliable correlation between the physical defects in the devices and the information given by the acoustic microscope.