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Soldering
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Proceedings Papers
ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 49-52, November 2–6, 2008,
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This case study shows a typical example of a manufacturing-chain-induced reliability problem. All participants of the chain do their work within specifications, but, looking at the system level, severe reliability problems have been observed. In order to get back into the system-level process window, several corrective actions are possible. In this case, the most promising approach is an improvement of the stitch bond robustness, combined with a clear user specification.
Proceedings Papers
ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 53-58, November 2–6, 2008,
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While considerable amount of researches and investigations have been made on lead-free solder joint reliability, limited number of literatures are available on the effect of gold content on lead-free solder joint performance. The challenges of lead-free solder/gold metallization interdiffusion during high temperature application/test are: gold embrittlement, intermetallics growth, void formation, and tin-whisker formation. Tin whiskers causing system failures in earth and space-based applications have been reported. This paper illustrates a few case histories of such challenges. The results confirmed that the synergistic effects of void formation, intermetallic compounds formation due to the thick gold plating, and coefficient of thermal expansion mismatch between organic and ceramic substrates resulted in brittle fracture of the solder joint. The tin whisker formation was attributed to the compressive stress in the tin solder material, which was caused by diffusion of the end-cap metallization, formation of intermetallics, and thermal cycling of the soldered components.
Proceedings Papers
ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 243-250, November 11–15, 2001,
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Two novel techniques to identify continuity failures in multi-layer substrates of flip-chip package are discussed. The first technique uses the custom designed and fabricated Package Substrate Probe Fixture (PSPF™). The fixture eliminates the traditional method of soldering directly to the package solder balls. This ensures that failures are not heat cured and the solder ball as well as the Ball Grid Array (BGA) pad are not detached from the package substrate during physical analysis. Also employed are beam-based systems that include both Focused Ion Beam (FIB) and Electron-beam (Ebeam) to detect Capacitive Coupling Voltage Contrast (CCVC) images. Voltage contrast imaging augments traditional optical inspection techniques using bright and dark field microscopy.
Proceedings Papers
ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 253-257, November 11–15, 2001,
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This article outlines an optimal approach for board level CSP failure analysis, where the chip and printed circuit board are analyzed as a single unit to determine the root cause of the board level failures. A technique using a combination of cross-section and parallel polishing is described in detail. This technique was developed to inspect key aspects of solder joint fatigue, which are solder joint height, pad dimensions, heating profiles or reflow, substrate warpage, and solder joint voids. This technique allows investigation of the above factors in a single sample preparation and readily arrive at the root cause solution in the minimum time. Results showed that package properties, the design of solder pads play the major role in determining how the fatigue behavior of solder joints will affect CSP component. Additional factors like nickel/gold and nickel palladium finishes were found to be more brittle and promote solder joint cracking.
Proceedings Papers
ISTFA2000, ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis, 373-376, November 12–16, 2000,
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High temperature gold/tin eutectic (80 Au/ 20 Sn) solder is used in manufacturing for multiple reasons. These motives may include the ability to post solder a part/device without reflow, high temperature field applications, and allow soldering to thick Au layers without the possibility of precipitating AuSn4 brittle intermetallics. In the following military case, Au/Sn eutectic was employed because of high temperature service and the guarantee of no occurrence of gold embrittlement when soldering to the thick Au outer plating. The Au was plated over an electroplated nickel (Ni) layer on a Kovar (iron/nickel/cobalt) housing. The soldering resulted in an extremely poor bond strength of a duroid circuit to the Kovar housing. The results showed contamination in the supplier’s electroplated Ni bath caused the plating to have poor bond strength. The failure occurred within the Ni plating layer.