Presentation slides for the ISTFA 2024 Tutorial session “Transmission Electron Microscopy.”

Presentation slides for the ISTFA 2024 Tutorial session “TEM Sample Preparation for Electron Microscopy Characterization and Failure Analysis of Advanced Semiconductor Devices.”

Presentation slides for the ISTFA 2024 Tutorial session “Transmission Electron Imaging AND Diffraction in an SEM (aka, STEM-in-SEM): What, Why, and How To Do This in Your Microscope.”

In the ever-increasing complexity of today’s state-of-the-art semiconductor structures, it is desirable to seek any advantage in the fault isolation and analysis paradigm to improve time to data. This paper discusses one such improvement where it is shown to be possible to target silicon (Si) devices, their metal contacts, or any other location in the wafer stack in a SRAM test structure from metal level 7 (M7) for transmission electron microscopy (TEM) sample fabrication using a modified sample geometry, focused ion beam (FIB) software targeting tools, and planning for failure analysis at the mask design stage. Electron beam inspection data was used to drive back to the location of interest in this example. The subsequent analysis shows a silicon and oxygen rich material creating an open contact defect signature.

The TEM sample preparation by Plasma focused ion beam (PFIB) for a 3D NAND sample with high aspect ratio (HAR) was investigated. Through the PFIB window delayering method, a nearly curtain-free and uniform thickness of TEM lamella could be obtained, addressing the issue of curtaining effectively. Moreover, the pre-treatment step for preparing the chunk of the region of interesting (ROI) out from wafer can be performed by PFIB automated procedures, which could promote the sample preparation efficiency. Through the PFIB window delayering method, TEM analysis of large-area HAR 3D NAND nanostructures becomes achievable.

Failure analysis for gate oxide breakdown is increasingly challenging as technology advances to smaller technology nodes. Previously, the cross-sectional passive voltage contrast (XPVC) technique has been successfully utilized in mature technology nodes to isolate gate oxide breakdown locations in complex polysilicon gate structures of planar transistors. However, as semiconductor technology advances, more intricate transistor structures such as FinFET are employed to improve device performance. This paper focuses on the application of the XPVC technique to metal gate structures and examines the challenges associated with its implementation in advanced technology nodes. We demonstrate the applicability of this method in 14nm FinFET devices in simulated gate oxide breakdown experiments showcasing successful sample preparation for subsequent Transmission Electron Microscopy (TEM) analysis.

We present a study of dislocation conductivity under forward bias in p-GaN/AlGaN/GaN heterojunctions on a GaN-on-Si substrate, which are part of every p-GaN HEMT structure. Conductive atomic force microscopy (C-AFM) is combined with structural analysis by scanning transmission electron microscopy (STEM) and defect selective etching (DSE). The density of conductive TDs was found to be 5 × 10 6 cm -2 , using semi-automatic measurements to gather larger statistics on a delayered HEMT sample. IV measurements show a shift in turn-on voltage at the leakage positions. To characterize the type of the conductive TDs, DSE with a KOH/NaOH melt was used. Three distinct etch pit sizes were observed after 5 s etch time, with large, medium and edge pits according to STEM characterization seemingly corresponding to screw, mixed and edge TDs, respectively. However, characterization by DSE etch pit size alone was found to be unreliable, as STEM TD typing of seven conductive TDs using two-beam diffraction conditions revealed mostly pure screw and mixed-type dislocations with medium-sized etch pits as origin of the observed leakage current. Our work highlights the limitations of DSE as a characterization method and recommends additional validation by STEM for each new material system, investigated layer, and etching setup. The implications of finding conductive TDs with screw-component under low forward bias conditions on device behavior and the limitations of the C-AFM method are discussed. Based on the results, it is not anticipated that the identified conductive TDs will have a substantial effect on a GaN HEMT device. Overall, this study provides important insights into the electrical properties of TDs and offers useful recommendations for future research in this area.

Advanced semiconductor devices are disrupting traditional failure analysis workflows and creating demand for instrumentation that enables flexible capabilities to address these technology inflections. Such trends can be observed across multiple development areas, including faster processing, increased memory bandwidth, and power delivery. In every case, shrinking structures, complex packaging architecture, and advanced materials drive the need for efficient, precise targeting for regions of interest (ROI) over a wide range of length scales. An important example is the implementation of wide-bandgap (WBG) semiconductors, such as SiC and GaN, in advanced power devices. Various complexities are introduced, not only in device architecture, but also in defectivity analysis by conventional methods. As a result, high quality and high throughput failure analysis is achieved with specialized use of several plasma focused ion beam (PFIB) species best suited to these materials. Here we demonstrate such sample preparation for workflows involving electrical failure analysis (EFA) and localization, cross-sectional and volume analysis using scanning electron microscopy (SEM), as well as lamella preparation for transmission electron microscopy for physical failure analysis (PFA).

Electrical characterization is a critical step in the failure analysis workflow, a sequence that often ends in high-resolution imaging in the transmission electron microscope (TEM). Scanning TEM electron beam-induced current (STEM EBIC) is a technique that effectively combines these methods by performing electrical characterization at each imaging pixel, with the electron beam acting as a local current source. This work highlights the specimen preparation technique using the Ga FIB system followed by post-FIB Ar ion milling for STEM EBIC analysis. We present STEM EBIC as a technique to evaluate the surface quality of the specimens and to characterize the electronic properties of advanced devices at high resolution. With STEM EBIC, inactive and active finFET structures were clearly distinguished and improvements in sample quality from post-FIB Ar ion milling were evident.

We demonstrate the effectiveness of combining top-down and cross-sectional electron beam induced current (EBIC) imaging with SEM nanoprobe analysis to identify subtle front-end defects in advanced FinFET technology. Our approach successfully localized a novel fin nanocrack defect that had previously eluded detection through conventional TEM imaging. This systematic resistive pMOS failure, observable only in memory arrays at 150°C, exemplifies the power of EBIC as an alternative to scanning capacitance microscopy for detecting dopant anomalies and subtle defects. The sample preparation and EBIC methodologies presented here are broadly applicable across CMOS technologies, offering a versatile approach to defect analysis.

Photoresist (PR) profiles tend to have deformation and shrinkage with typical transmission electron microscopy (TEM) analysis method using a focused ion beam scanning electron microscope (FIB-SEM) and TEM. The elevated temperatures during sample preparation and TEM analysis are believed to contribute to these issues. This study evaluates the effectiveness of cryogenic workflow in mitigating PR profile shrinkage by employing cryo-focused ion beam (Cryo-FIB) and cryo-transmission electron microscopy (Cryo-TEM). Comparative experiments were conducted at room temperature and cryogenic conditions, demonstrating that full cryogenic workflow reduces the shrinkage of PR, bottom anti-reflective coating (BARC), and line critical dimension (CD). Our findings indicate that both the sample preparation and analysis temperatures influence PR profiles. This study highlights how the full cryogenic workflow significantly minimizes shrinkage, providing more accurate PR profile measurements.

This study investigates the application of 3D electron tomography to enhance transmission electron microscopy (TEM)-based failure analysis of 3D FinFET transistors. Traditional TEM analysis is challenged by projection effects due to the thickness of the sample, complicating accurate defect characterization in miniaturized semiconductor structures. The defects seen by conventional (2D projection) TEM imaging are unclear and difficult to interpret. Leveraging scanning transmission electron microscopy (STEM) and energy dispersive X-ray spectroscopy (EDS) tomography techniques, the study presents detailed examinations of two semiconductor samples exhibiting high leakage currents. Results reveal etched-out epitaxial regions subsequently filled with gate materials, critical for understanding device failure. By digitally reconstructing TEM lamellae in three dimensions, this approach overcomes projection artifacts and precisely localizes defects. The findings underscore the efficacy of 3D electron tomography in semiconductor failure analysis, offering insights crucial for improving device reliability and manufacturing processes in advanced semiconductor technologies.

This paper presents an automated focused ion beam (FIB) workflow that revolutionizes FIB-TEM sample preparation for semiconductor analysis, particularly for NAND and DRAM devices. This system integrates with Helios 5 HX and Helios 6 HX platforms to achieve consistent, hands-free sample preparation down to ~10 nm thickness. Our approach transforms traditional manual processes into automated workflows through comprehensive best-known method (BKM) templates, custom recipes, and proprietary code development in AutoTEM and iFast software architectures. The system features advanced machine vision algorithms and custom hardware components that enable precise sample coordination, allowing for both vertical and perpendicular TEM sample preparation from 3D structures at any wafer depth. Implementation results demonstrate significant improvements over manual processes, including thousands of hours in workforce savings, reduced material waste, faster throughput, improved data consistency, and minimized human error in DRAM and NAND structural analysis.

A series of power supply line controller failures at Analog Devices Incorporated (ADI) exhibited abnormal output voltage and quiescent current symptoms. Our failure analysis revealed a gate-to-drain/source tungsten spur defect, which required a sophisticated multi-step detection process. The investigation combined several advanced techniques: light emission microscopy (LEM) and optical beam induced resistance change (OBIRCH) identified the failing circuit, passive voltage contrast (PVC) located the affected transistor, and nanoprobing with electron beam induced resistance change (EBIRCh) pinpointed the gate-to-source/drain leakage location. Focused ion beam (FIB) cross-sectioning proved crucial for physical analysis, as conventional chemical deprocessing would have destroyed the tungsten spur and potentially misidentified the defect as electro-static discharge damage. Transmission electron microscopy confirmed the spur's composition as tungsten, and subsequent fabrication investigation traced the root cause to a titanium nitride barrier breach at the contact bottom, occurring where contacts intersect with spacer nitride. The issue was resolved through critical dimension tightening at the fabrication site.

The role of scanning transmission electron microscopy (STEM) in failure analysis has been growing since the introduction of advanced technology nodes (10-nm and beyond), in which transistors (FinFET and nanosheets) have become much smaller and more complex. Four-dimensional scanning transmission electron microscopy (4D-STEM) is a new electron diffraction technique that expands conventional STEM imaging and EDX mapping to enable phase and orientation mapping of crystalline and amorphous phases in deposited thin films at the nanometer resolution. The enhancement of electron diffraction data by beam precession is then fundamental for higher accuracy and precision, especially in the case of strain measurements. The power of precession-assisted 4D-STEM analysis is demonstrated using the example of Germanium separation from within a Ge-rich GeSbTe layer in a phase memory device and with the example of tensile and compressive strain in a Samsung 5-nm technology node. These advanced electron diffraction measurements are now accessible to a broad range of users in routine analytical procedures due to unprecedented high levels of automation and synchronization in the new analytical STEM instrument, TESCAN TENSOR.

Power MOSFETs are electronic devices that are commonly used as switches or amplifiers in power electronics applications such as motor control, audio amplifiers, power supplies and illumination systems. During the fabrication process, impurities such as copper can become incorporated into the device structure, giving rise to defects in crystal lattice and creating localized areas of high resistance or conductivity. In this work we present a multiscale and multimodal correlative microscopy workflow for the characterization of copper inclusions found in the epitaxial layer in power MOSFETs combining Light Microscopy (LM), non-destructive 3D X-ray Microscopy (XRM), Focused-Ion Beam Scanning Electron Microscopy (FIB-SEM) tomography coupled with Energy Dispersive X-ray Spectroscopy (EDX), and Transmission Electron Microscopy (TEM) coupled with Electron Energy Loss Spectroscopy (EELS). Thanks to this approach of correlating 2D and 3D morphological insights with chemical information, a comprehensive and multiscale understanding of copper segregations distribution and effects at the structural level of the power MOSFETs can be achieved.

Static random-access memory (SRAM) is a type of device that requires the highest reliability demands for integration density and process variations. In this study, we focus on single bit cell SRAM failures. These failures can be categorized as Hard bit cell failure, where bit cells fail the read or write operation under both higher and lower supply voltages, and Soft Bit cell failure, where failures occur at either higher or lower voltage. The analysis on SRAM Soft failure is further divided as VBOX High and VBOX Low failure, which depends on the failure mode supply voltage. With transistor dimensions continuously shrinking, the analysis of SRAM errors imposes tremendous challenges due to their small footprint. In this paper, a thorough failure analysis procedure is described for solving an SRAM yield loss issue. Different analysis techniques were applied and compared to narrow down the failure to the final root cause, including nanoprobing, Focus Ion Beam (FIB) cross-section, Scanning Spreading Resistance Microscopy (SSRM), Transmission Electron Microscopy (TEM), Electron Energy Loss Spectroscopy (EELS), Scanning Capacitance Microscopy (SCM), and stain etch.

The growing demand for flash memory in the artificial intelligence and big data industries has driven the development of Negative AND (NAND) gates. To increase yield and cost competitiveness, NAND has evolved to stack gates vertically, resulting in vertical NAND (VNAND) technology. However, this advancement has led to challenges, such as high aspect ratio-related difficulties and word line (WL) metal Tungsten (W) substitution process defects. In this study, we investigated Voltage Blocking Oxide Barrier (VBB) defects in VNAND cells under high-temperature conditions using in-situ heating TEM. By artificially creating VBB defect environments within VNAND cells and analyzing structural and chemical changes, we identified VBB defects expression phenomenon caused by residual HF(g) in metal voids during post-metal replacement processes. Our findings offer insights into defect-inducing heat treatment conditions affecting VBB in VNAND devices and propose directions for next-generation NAND flash processes.

Photoresist (PR) profiles tend to have deformation and shrinkage with typical transmission electron microscopy (TEM) sample preparation methods using a focused ion beam scanning electron microscope (FIB-SEM). As the temperature increases during the TEM sample preparation, it may lead to deformation and shrinkage in PR profiles. In this study, we analyze the impact when performing the sample preparation at a cold temperature using a cryo-FIB to minimize deformation and shrinkage issues. To test this methodology, the TEM sample preparation process was performed under different conditions. From these experiments, the TEM results with full cryo conditions showed that the PR line to space ratio was closest to the target, which is the sample’s real line to space ratio (1:1), and the bottom anti-reflective coating (BARC) shrinkage was minimized.

Advanced memory technologies are in demand with phase change memory (PCM) devices as a forefront candidate. For successful characterization by transmission electron microscopy (TEM) for failure analysis and device development, an accurate and controllable thinning of TEM specimens is critical. In this work, TEM specimens from a GeTe-based PCM device at a partial SET state were prepared using a Xe plasma focused ion beam (pFIB) and polished to electron transparency using Ar ion beam milling. We will highlight the differences between Ga focused ion beam (FIB) and Xe pFIB TEM specimen preparation, the benefits of post-pFIB Ar ion beam milling, and show TEM results of the effects of partial SET programming of the GeTe PCM device.